Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2009 Research Summary

Fundamental Redundancy versus Power Tradeoff in Standby SRAM

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Animesh Kumar, Huifang Qin, Jan M. Rabaey and Kannan Ramchandran

National Science Foundation CCR-0330514 and Gigascale Systems Research Center GSRC Marco

We study the problem of reducing power during data-retention in a standby static random access memory (SRAM). For successful data-retention, the supply voltage of an SRAM cell should be greater than a critical data retention voltage (DRV). Due to circuit parameter variations, the DRV for different cells on the same chip exhibits variation with a distribution having diminishing tail. For reliable data retention, the existing low-power design uses a worst-case technique in which a standby supply voltage that is larger than the highest DRV among all cells in an SRAM is used. Instead, our approach uses aggressive voltage reduction and counters the ensuing unreliability through fault-tolerant memory architecture. The main results of our work are as follows: (1) We establish fundamental bounds on the power reduction in terms of the DRV-distribution using techniques from information theory. For the DRV-distribution of an experimental test-chip (see Figure 1), we show that 49% power reduction with respect to (w.r.t.) the worst-case is a fundamental lower bound while 40% power reduction w.r.t. the worst-case is achievable by using a practical bounded-distance decoding scheme. (2) We study the power reduction as a function of the block-length for low-latency codes since most applications using SRAM are latency constrained. We propose a reliable memory architecture based on the Hamming code for the next test-chip implementation with a predicted power reduction of 33% while accounting for coding and latency overheads.

Figure 1
Figure 1: Empirical DRV-distribution: the intra-chip DRV varies from 70 to 190 mV for the 90 nm CMOS technology [1]

Figure 2
Figure 2: Power per useful bit bounds: this figure illustrates the power per useful bit as a function of the supply voltage. The function p(vS) is the probability that any particular cell will have a DRV larger than the supply voltage. For example, at vS = 200 mV, all the cells are error-free and p(vS) = 0. The minimum values of fundamental upper and lower bounds are 40% and 49% lower w.r.t. worst-case.

[1]
H. Qin, R. Vattikonda, T. Trinh, Y. Cao, and J. Rabaey, "SRAM Cell Optimization for Ultra-Low Power Standby Operation," Journal of Low Power Electronics, December 2006.