Scalability of On-Chip Transmission Lines
Ling Zhang, Chung-Kuan Cheng and Ernest S. Kuh
The goal of this research is to develop and optimize an on-chip global signaling scheme with transmission line to achieve high speed and low power communication. As technology scales, interconnects become one of the most critical factors in determining the digital system speed and power consumption. Transmission lines offer the potential to break the wall that blocks the interconnect performance since the approach allows the signal to travel at the speed of light in the medium, and the signal toggles as waves instead of enforced electronic charges and thus saves power.
In order to make the transmission line competitive in practice, we need to design the wire dimension considering attenuation so that the received signal is large enough to be immune from crosstalk and noise. We can pre-emphasize the signal at the driver or equalize at the receiver to alleviate the inter-symbol interference. The compensation can be carried out by active devices or passive RLC components to save power.
We need to model and design the drivers/receivers since their delay and bandwidth can become limiting factors of the overall performance. To increase the throughput of the communication in a given physical space, we would like to shrink the cross section of the transmission lines. The length of wire segments can be reduced by inserting transceivers at the expense of extra power consumption.
We plan to develop an optimization flow to investigate the scalability of the scheme for technology from 90 nm to 22 nm.