Josephson-CMOS Hybrid Memories
Heejoung Park, Xiaofan Meng, Hongfei Ye, Stephen R. Whiteley and Theodore Van Duzer
Josephson-CMOS hybrid random-access memories (RAMs) have the potential to remove the memory bottleneck faced by Josephson digital technology. We use high-density MOS memory cells and access them by high-speed superconductive devices. The operation at 4 K of standard commercial 0.25 mm and 0.18 µm CMOS has been extensively explored and an accurate model for digital applications has been established.
We have shown experimentally that the total access time for a single bit in the 64-kb memory system using 0.25 mm CMOS and Josephson current density of 2.5 kA per cm square is 0.5 ns, and this agrees with simulations. Bump-bonding was used to connect the two chips [1,2].
During 2009, we will fabricate a more complete representation of a 64 kb memory, which will include both writing and reading of complete words, and measure the access times. We will also explore the feasibility of embedding CMOS memory chips in a silicon wafer and fabricating the Josephson circuits on the planarized surface thereof.
- Q. Liu, K. Fujiwara, X. Meng, S. R. Whiteley, T. Van Duzer, N. Yoshikawa, Y. Thakahashi, T. Hikita, and N. Kawai, “Latency and Power Measurements on a 64-kb Hybrid Josephson-CMOS Memory,” IEEE Trans. Appl. Superconduct., Vol. 17, June 2007, pp. 526-529.
- K. Fujiwara, Q. Liu, X. Meng, T. Van Duzer, and N. Yoshikawa, “Half-Nanosecond Latency Measurement on a 64-kbit Josephson-CMOS Memory,” Extended Abstracts of the International Superconductive Electronics Conference, Washington, DC, June 2007.