Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2009 Research Summary

Design of LDPC Decoders for Low Error Rate Performance

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Zhengya Zhang, Pamela Lee, Lara Dolecek1, Borivoje Nikolic, Venkat Anantharam and Martin Wainwright

National Science Foundation CCF-0635372, Marvell, Intel, Infineon Technologies and UC MICRO

Low-density parity-check (LDPC) codes have been demonstrated to perform very close to the Shannon limit when decoded iteratively. Sometimes excellent performance is only observed up until a moderate bit error rate (BER); at a lower BER, the error curve often changes its slope, manifesting a so-called error floor. Such error floors are a major factor in limiting the deployment of LDPC codes in high-throughput applications.

We design a parallel-serial architecture to map the decoders of structured LDPC codes to a hardware emulation platform. Experiments in the low BER region provide statistics of the error traces, which are used to investigate the causes of the error floors [1]. Different classes of errors cause error floors. But even with an optimal implementation, the error floors are inevitable due to certain combinatorial structures of the LDPC code, termed absorbing sets [2]. The effect of absorbing sets in determining the error floor level is influenced by implementation. Conventional decoder implementations tend to induce low-weight weak absorbing sets, and, as a result, elevate the error floor. We propose alternative quantization schemes and demonstrate seemingly inferior algorithms that alleviate the effects of weak absorbing sets [3]. Furthermore, we can exploit the structure of absorbing sets with a redesigned message-passing decoder to escape such local minimum states [4]. The investigative approach and ASIC design approach are unified using a Simulink-based design flow. Rapid prototyping allows us to concurrently explore the algorithmic, architectural, and implementation spaces in order to optimize the decoder design.

Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. Wainwright, "GEN03-6: Investigation of Error Floors of Structured Low-Density Parity-Check Codes by Hardware Emulation," IEEE GLOBECOM Global Telecommunications Conference, November 2006, pp. 1-6.
L. Dolecek, Z. Zhang, V. Anantharam, M. Wainwright, and B. Nikolic, "Analysis of Absorbing Sets for Array-based LDPC Codes," IEEE International Conference on Communications, June 2007, pp. 6261-6268.
Z. Zhang, L. Dolecek, M. Wainwright, V. Anantharam, and B. Nikolic, "Quantization Effects in Low-Density Parity-Check Decoders," IEEE International Conference on Communications, June 2007, pp. 6231-6237.
Z. Zhang, L. Dolecek, B. Nikolic, V. Anantharam, and M. J. Wainwright, "Lowering LDPC Error Floors by Postprocessing," Proc. IEEE GLOBECOM, New Orleans, LA, November 2008.
P. Lee, L. Dolecek, Z. Zhang, V. Anantharam, B. Nikolic, and M. J. Wainwright, "Error Floors in LDPC Codes: Fast Simulation, Bounds, and Hardware Emulation," ISIT International Symposium on Information Theory, July 2008, pp. 444-448.

1Massachusetts Institute of Technology