Sense Amplifier-based Pass Transistor Logic (SAPTL)
Louis Poblete Alarcon, Tsung-Te Liu and Jan M. Rabaey
Gigascale Systems Research Center
The SAPTL is an alternative circuit topology that allows the reduction of energy per operation via voltage scaling even in the presence of leakage .
It allows aggressive supply voltage scaling since the threshold voltages of the "stack" transistors can be decoupled from the system subthreshold leakage current, allowing for very low threshold voltages. This also allows the stack transistors to remain in the superthreshold region.
In addition, the differential signaling used by the SAPTL lends itself to synchronous and asynchronous operation  and the inherent layout regularity points to the SAPTL as a very good candidate for robust ultra low energy operation.
Figure 1: The SAPTL architecture
Figure 2: The 1.25 mm x 1.25 mm 90 nm synchronous SAPTL test chip with 31 SAPTL experiments
Figure 3: The 3 mm x 3 mm 90 nm self-timed SAPTL test chip with 101 SAPTL experiments
- L. Alarcón, T.-T. Liu, M. Pierson, and J. Rabaey, “Exploring Very Low-Energy Logic: A Case Study,” Journal of Low Power Electronics, Vol. 3, No. 3, December 2007, pp. 223–233.
- T.-T. Liu, L. Alarcón, M. Pierson, and J. Rabaey, “Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic,” Proceedings of International Symposium on Asynchronous Circuits and Systems (ASYNC), 2008.