Double-Gate MOSFET Modeling: Asymmetric DG (BSIM)
Darsen Duane Lu, Chung-Hsun Lin, Mohan Vamsi Dunga, Tianjiao Zhang, Chenming Hu and Ali Niknejad
The independent gate architecture of DG (Figure 1) allows the designer to tune the threshold voltage of the DG-FET by changing the back gate voltage without the use of body doping. This gives the circuit designers additional flexibility to resolve the tradeoff between speed and power. Currently, the existing compact models do not address independent gates. The goal of this project is to develop a compact model for the asymmetric independent DG-FET.
We have finished the development of the core I-V and C-V development for independent-gate DG-FET . Various real device effects such as short channel effects and velocity saturation have been incorporated in the model. The model is successfully implemented in the Verilog-A language and can be used for circuit design.
So far the model accurately describes the I-V and C-V of the device as long as only one surface is biased in a strong inversion region. Our current effort is to accurately model the bias range where both the front and back surfaces are biased in strong inversion. This bias range is important for applications such as FinFET-based SRAM cells  and independent-gate mixers .
Figure 1: (a) Bulk FinFET with two independent gates; (b) SOI FinFET with independent gates; (c) Back-gated SOI MOSFET
Figure 2: Vt-roll off for the independent-gate FinFET is fitted very well
Figure 3: The effect of body doping on the threshold voltage (VTH) is captured by the model
- D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad, and C. Hu, "A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation," IEDM, 2007 (to appear).
- Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King, and B. Nikolic, "FinFET-Based SRAM Design," Proc. ISLPED, 2005, p. 2.
- L. Matthew et al., "CMOS Vertical Multiple Independent Gate Field Effect Transistor (MIGFET)," Proc. SOI Conf., 2004, p. 187.