Automatic Clock Gate Synthesis
Aaron P. Hurst, Robert K. Brayton and Andreas Kuehlmann
The goal of this project is to develop a scalable method for extracting and synthesizing clock gating logic. The total amount of dynamic power required to distribute a clock signal is currently as large as 30-40% of the overall power consumption. Clock gating involves inserting combinational logic along the clock path to prevent the unnecessary switching of sequential elements and reduce this total. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically; we seek to develop an efficient automatic method that is suitable for gate-level representations. Our current approach utilizes simulation and satisfiability testing to extract potentially useful functions from the existing logic. The final gating function can then be implemented with a small and predictable amount of logic. This is an improvement over existing techniques in the logic-level application, problem scalability, and minimal design perturbation.