Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

Large-Scale Assembly of Semiconducting Nanowires for Integrated Nanoelectronics

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Zhiyong Fan, Johnny Ho, Zachery Jacobson, Roie Yerushalmi, Robert Alley, Haleh Razavi and Ali Javey

Controlled and uniform assembly of "bottom-up" nanowire (NW) materials with high scalability presents one of the significant bottleneck challenges facing the integration of nanowires for electronic circuit applications. Here, we demonstrate wafer-scale assembly of highly ordered, dense, and regular arrays of NWs with high uniformity and reproducibility through a simple contact printing process. The assembled NW pitch is shown to be readily modulated through the surface chemical treatment of the receiver substrate, with the highest density approaching ~8 NW/µm, ~95% directional alignment and wafer-scale uniformity. Furthermore, we demonstrate that our printing approach enables large-scale integration of NW arrays for various device structures on both Si and plastic substrates, with a controlled semiconductor channel width, and therefore ON current, ranging from a single NW (~10 nm) and up to ~250 µm, consisting of a parallel array of over 1,250 NWs.

Figure 1
Figure 1: (a) SEM images of GeNWs (d~30 nm) printed on a Si/SiO2 substrate showing highly dense and aligned monolayer of nanowires. (b) Optical images of double layer printing for SiNW (d~30 nm) cross assembly. (c) Large scale and highly uniform parallel arrays of aligned GeNWs (d~30 nm) were assembled on a 4" Si/SiO2 wafer by contact printing. The inset is an SEM image of the printed NW film, showing a density of ~ 7 NW/µm.