Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

Spacer Gate Lithography for Reduced Variability Due to Line Edge Roughness

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Xin Sun and Tsu-Jae King Liu

Variability in transistor performance is one of the major challenges for continued scaling of CMOS technology. As transistor gate lengths are scaled down, line edge roughness (LER) is not reduced commensurately. At the same time, thermal process budgets are reduced to achieve shallower and more abrupt junctions, so that the effects of gate LER become increasingly significant.

The effect of line edge roughness (LER) on bulk-Si MOSFET performance is studied using three-dimensional (3D) device simulations [1]. Spacer gate lithography is compared to conventional gate lithography. The effects of source/drain placement and spacer width variation are also investigated. The effects of LER parameters such as correlation length on MOSFET performance are studied for both the conventional gate lithography and spacer gate lithography. The simulation results indicate that spacer gate lithography dramatically reduces LER-induced variation and variability is well suppressed with gate-length scaling, even if LER does not scale.

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