Effects of Stacks in 45 nm CCMOS
Kenneth Duong, Borivoje Nikolic and Liang Teck Pang
Clocked storage elements (CSEs) in digital IC circuits take up a large percentage of chip area and cycle time. As technology nodes scale down, process variations increasingly affect important CSE timing parameters including clock-to-q delay, and setup/hold times. A test chip is being developed in order to observe and analyze these effects, with the motivation of finding the most robust (with respect to variability) CSE implementations. Ring oscillator arrays will be used to characterize the variation of commonly-used CSE building blocks, both across chip and die-to-die. One interesting outcome of these experiments will be the characterization of the difference in variability due to the switching of different transistors in a stack. In order to compare overall CSE topologies in terms of variability, a delay measurement circuit has been designed to measure the timing parameters of large CSE arrays with 1 picosecond resolution and will also be implemented on this test chip.