Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Precision Timed (PRET) Machines

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Hiren D. Patel, Shanna-Shaye Forbes, Dai Bui, Isaac Liu and Edward A. Lee

The trend in computing over the years exemplifies abstraction as an essential principle towards tackling complexity. However, the techniques used have commonly emphasized functionality and performance, not timing. This is particularly true for processor design, where computer architects, language designers, compiler programmers, etc. focus on correct functionality while improving the average case performance by using sophisticated techniques such as advanced pipelining, caching, speculation, and prediction. As a consequence, processor architectures are faster as per average case performance, and in our opinion, unpredictable with respect to meeting timing guarantees. In the general purpose architecture arena, the disagreement between performance and predictable timing can be tolerated, but in the embedded space, timing and predictability are far more important and thus critical to the correct functioning of an embedded system. Therefore, preserving the property of predictable timing along with functionality in our abstraction principles is necessary for the correct design of an embedded system, but lacking at several abstraction layers such as programming languages, operating systems, compilers, networks, and processor architectures. Our vision with this project is to explore and reintroduce predictable timing as a first-class citizen of embedded processor architectures, or what we term precision timed (PRET) machines.

As a start, we have a bare-bones processor implementation of the Renesas H8300 with an additional deadline instruction mimicking a soft real-time constraint. This, however, is not the first of the recent processors that claims predictable timing as evidenced by JOP [1] and SPEAR [2]. Moreover, there is a whole class of reactive processors [3, 4] that also propose alternatives for predictable timing. So, as a part of our exploration we hope to validate whether the approach we have currently undertaken (deadline instruction added to the Renesas H8300) can not only deliver precise timing but also reasonable performance. To do so, our investigations will focus on: (1) incorporating traditional architectural components such as interleaved pipelines, memory hierarchies and additional hard-time instructions to improve performance while still maintaining timing predictability; (2) introducing concurrency management; (3) a system-level analysis framework for performance and timing integrated with the Metro II [5] framework; and (4) a hardware communication interface mechanism that does not disrupt timing guarantees. With these research directions, we hope to provide an embedded processor architecture with predictable timing that is downloadable on an FPGA as a soft core, a preliminary system-level exploration framework, concurrency management, and an application of a related project called Programming Temporally Integrated Distributed Embedded Systems (PTIDES) [6] on a PRET machine.

[1]
M. Schoeberl, "JOP: A Java Optimized Processor for Embedded Real-Time Systems," PhD thesis, Vienna University of Technology, 2005.
[2]
M. Delvai, W. Huber, P. Puschner, and A. Steininger, "Processor Support for Temporal Predictability--The SPEAR Design Example," Proceedings 15th Euromicro Conference on Real-Time Systems, 2003, pp. 169-176.
[3]
X. Li and R. Hanxleden, "The Kiel Esterel Processor--A Semi-Custom, Configurable Reactive Processor," Synchronous Programming-SYNCHRON, No. 04491, 2005.
[4]
Z. Salcic, D. Hui, P. S. Roop, and M. Biglari-Abhari, "HiDRA Reactive Multiprocessor Architecture for Heterogeneous Embedded Systems," Microprocessors and Microsystems, Vol. 30, No. 2, 2006, pp. 72-85.
[5]
A. Davare, D. Densmore, T. Meyerowitz, A. Pinto, A. Sangiovanni-Vincentelli, G. Yang, H. Zeng, and Q. Zhu, "A Next-Generation Design Framework for Platform-Based Design," Conference on Using Hardware Design and Verification Languages (DVCon), February 2007.
[6]
Y. Zhao, J. Liu, and E. A. Lee, A Programming Model for Time-Synchronized Distributed Real-Time Systems," IEEE Real Time and Embedded Technology and Applications Symposium, 2007, pp. 259-268.