Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Towards an Automated Mapping from a Timed Functional Specification to a Timed Architecture

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Hugo Andrade and Hiren Patel

Embedded systems are often used in applications that perform either soft real-time or hard-real time tasks. Throughout the years, however, many abstraction techniques used to mitigate the complexity of embedded systems design have emphasized functionality over predictable timing. As a result, there are only a handful of embedded processors that support predicable timing. Two such examples are the REMIC [1] and KEP [2] processors; both are reactive processors, based on the synchronous language semantics of Esterel. A reactive processor can be simply defined as one that reacts in a fast and efficient manner to an external event [1], and one that predictably offers exact timing for these reactions.

It is important to provide a model of computation that supports explicit timing and concurrency, and also to have an architecture that supports these characteristics of the model of computation. Current research in the CHESS group is focused on the development of a Precision Timed Machine (PRET) [3] which is an embedded processor architecture that is envisioned to support predictable timing without forgoing performance.

The objective of this project is to use LabVIEW [4] Embedded's platform-based design methodology as a model of computation to be mapped to PRET's single core architecture. Timing and concurrency for LabVIEW's mapping to PRET will be implemented with multithreading. A method of determining whether or not the concurrent threads will violate PRET's timing guarantees will also be estimated. This project will identify requirements for both the PRET architecture and the LABVIEW model of computation to ensure that such a mapping can be done correctly, consistently, and efficiently.