Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Layout Optimization based on a Generalized Process Variability Model

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Qian Ying Tang, Paul David Friedberg, George Cheng and Costas J. Spanos

The growing impact of process variation on circuit performance requires statistical design approaches in which circuits are designed and optimized subject to an estimated variation. As it is recently shown, what is often referred to as "spatial correlation" is an artifact of un-modeled residuals after the decomposition of deterministic variation components across the wafer and the die [1]. Consequently, a more accurate representation of process variability is to generate any apparent spatial correlation as the artifact of identified deterministic components. By assuming deterministic variability components of parabolic shape across the wafer and the die, the position-dependent joint distribution of critical device parameter W, L, and vth is estimated and incorporated into the formulation of circuit path delays. A transistor-level optimization that finds the optimal transistor width is then carried out for yield optimization. Optimization on an 8-bit Ladner-Fischer adder shows a yield improvement of almost 50% using the new, more realistic variability.

A layout generation tool is being constructed to incorporate the optimization procedure into the standard design flow. Custom circuit layouts are subjected to design rules to extract the margins allowed for each transistor active edge movement, prior to sizing optimization. The optimized layout can be subjected to further verification to account for any additional layout dependant effects.

Figure 1
Figure 1: (a) Comparison of the spatial correlation based design and the corresponding deterministic design; (b) Comparison of the generalized variability model based design and the corresponding deterministic design

Figure 2
Figure 2: Program flow of the layout generation tool

[1]
P. Friedberg, G. Cheng, Q. Y. Tang, and C. J. Spanos, "Modeling Micron-Scale Gate Length Variation and Spatial Correlation," SPIE International Symposium on Microlithography, March 2007.
[2]
Q. Y. Tang, P. Friedberg, G. Cheng, and C. J. Spanos, "Circuit Size Optimization with Multiple Sources of Variation and Position Dependant Correlation," SPIE International Symposium on Microlithography, March 2007.
[3]
S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz, "A Heuristic Method for Statistical Digital Circuit Sizing," 31st SPIE International Symposium on Microlithography, February 2006.
[4]
M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching Properties of MOS Transistors," IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, October 1989, pp. 1433-1439.