Low Subthreshold Swing Transistors
Pratik Ashvin Patel, Anupama Bowonder and Chenming Hu
Power supply (Vdd) scaling has slowed down to a crawl since the 130 nm node. Not coincidentally, for the first time since the 0.5 µm node when 5 V was still the standard Vdd from node to node, power consumption has reappeared as a leading design challenge. A comprehensive long term low-power scenario has to involve a device technology that is friendlier to low-Vdd-scaling than the MOSFET, i.e., one that is not subject to the 60 mV/decade subthreshold-swing limit.
Gate induced band-to-band-tunneling (BTBT) is not subject to the 60 mV/decade limit because charge carriers do not flow over a potential barrier, but rather tunnel through it. All previous studies of BTBT-based transistors have relied on the same basic structure--the gated PN diode. However, all valid data have shown disappointingly low drive current. We are investigating a new structure that, according to 2D device simulation, could provide very attractive on-current and Ion/Ioff ratio and is scalable to 0.2 V, thus improving the prospect of tunnel transistor as a low voltage/power device that can help to extend the limit of IC density growth. Experimental fabrication is currently underway on this new tunnel structure.