Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

Flash Annealing to Enable Formation of Ultra-Shallow Junctions and Its Integration with High-k/Metal-Gate MOSFETs

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Pankaj Kalra and Tsu-Jae King Liu

The formation of ultra-shallow junctions (USJs) with sub-15 nm depth and sheet resistance below 1000 ohm/sq. is a critical front-end processing challenge for sub-45 nm CMOS technology generations. Flash annealing and laser annealing are two candidate processes to replace conventional spike annealing, because they provide for higher dopant activation (peak temperature in the range 1300°C - 1400°C) and minimal dopant diffusion (annealing time in the range ~ms down to ns). However, very little has been reported on the effects of ms annealing on the performance and reliability of MOSFETs with metal-gate/high-k stacks.

P+ USJ studies were first done on blanket wafers with various combinations of low-energy boron implants, pre-amorphization implants, co-implants, and post-implant annealing conditions. Figure 1 summarizes the experimental results, which shows that spike annealing results in junctions that are too deep for sub-45 nm CMOS, even with co-implantation, due to transient enhanced diffusion. On the other hand, it is possible to achieve Xj in the range ~12-15 nm with Rs ~1 k ohm/sq. via flash annealing, which is adequate for 32 nm technology.

Furthermore, a detailed investigation of the effects of flash annealing on MOSFETs with Hf-based dielectric and metal gate stack is done [1]. The key findings are: (a) flash annealing can retain high-k/metal gate stack integrity while achieving USJ benefits, (b) interface is degraded which results in mobility loss, but (c) optimized post-metalization anneal helps to recover effectively the mobility loss by improving interface quality as shown in Figure 2.

Figure 1
Figure 1: Sheet resistance (Rs) determined by non-contact method vs. junction depth (Xj), for ultra-shallow p+ (Boron) junctions formed with either flash or spike annealing

Figure 2
Figure 2: Mobility loss as seen in a flash-annealed nMOSFET is recovered by an appropriate optimized post-metallization anneal

P. Kalra et al., IEEE International Electron Devices Meeting, 2007.