Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

Schottky Barrier Engineering for Low Contact Resistance Technology

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Pankaj Kalra and Tsu-Jae King Liu

The objective of this work is to identify means for achieving low barrier height so as to minimize the impact of contact resistance for sub-20 nm gate length CMOS technologies. Various techniques for reducing the effective Schottky barrier height of a metal-to-semiconductor contact are currently being investigated. We are studying image-force lowering as a possible mechanism to reduce barrier height. The phenomenon of dopant segregation during silicidation achieves very high active dopant concentrations in Si resulting in a large image-force field induced barrier lowering at the silicide-semiconductor interface. In most metal-silicon material systems, the barrier height does not correlate well with the metal work function, due to interface states, which pin the Fermi level resulting in a large effective Schottky barrier height. In order to de-pin the Fermi level of the metal, we are investigating passivation of metal-semiconductor interface (eliminating interface states) using species such as Se, S, and N. These can be introduced into the semiconductor by ion implantation, and then "piled up" at the silicide-semiconductor interface during the silicidation process.

Initial results have shown that NiSi to n-Si barrier height can be reduced by 150 meV with nitrogen. More species are being investigated to further lower the barrier.