Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

Broadband LNA Design Employing Noise and Distortion Cancellation (COGUR)

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Ali Niknejad and Wei-Hung Chen

The emerging 4G telecom system envisages ubiquitous wireless connectivity that supports multiple radio standards across multiple frequency bands and features reconfigurability for agile service switching and adaptive power consumption in response to the radio dynamics [1]. One key challenge in bringing out a multi-standard multi-mode front-end resides in fulfilling the high linearity and low noise over a wide frequency range [2]. Even in a "digital" receiver application, employing discrete-time signal processing, a linear front-end amplifier is required to reject the noise and relax the performance of the subsequent samplers [3]. The straight solution for multi-standard multi-mode front-ends employs reactive tuning and multiple receiving paths at cost of die and board area, high pin count, and lack of reconfigurability. Recent demonstration of ultra-wideband (UWB) LNAs ranging from several hundreds of MHz up to 10 GHz suggests an alternative that uses a single LNA for contiguous broadband signal receiving and has achieved comparable performances to its narrow-band counterparts by exploiting high fT /fmax transistors available from nano-scale CMOS.

In this project, we investigate the third-order linearity enhancement by canceling the second- and third-order distortions of the LNA circuit through multiple techniques. We present a broadband inductorless LNA circuit topology suitable for simultaneous noise and distortion cancellation and capable of low noise figure and high IIP3 at the same time. The proposed LNA topology also features great reconfigurability of trading LNA power consumption off other designated performance metrics such as noise figure, linearity, and gain. Manufactured in 0.13 µm CMOS technology, the prototype noise and distortion-canceling LNA achieved a peak IIP3 of +16 dBm and a noise figure below 2.6 dB over a wide bandwidth from 800-2100 MHz [4]. It uses nominal supply voltage of 1.5 V and regular Vt transistors. A maximum current of 11.6 mA is consumed in the above high performance mode and can be reduced if the required LNA dynamic range also reduces.

Figure 1
Figure 1: LNA chip microphotograph

T. B. Zahariadis, "Migration Toward 4G Wireless Communications," IEEE Wireless Comms., Vol. 11, No. 3, June 2004, pp. 6-7.
M. Brandolini et al., "Toward Multistandard Mobile Terminals--Fully Integrated Receivers Requirements and Architectures," IEEE Trans. Microwave Theory and Tech., Vol. 53, No. 3, Part 2, March 2005, pp. 1026-1038.
R. B. Staszewski et al., "All-Digital TX Frequency Synthesizer and Discrete-Time Receiver for Bluetooth Radio in 130-nm CMOS," IEEE J. Solid-State Circuits, Vol. 39, No. 12, December 2004, pp. 2278-2291.
W.-H. Chen et al., "A Broadband Highly Linear CMOS LNA Employing Noise and Distortion Cancellation," Proc. IEEE RFIC Symposium, Honolulu, HI, June 2007, pp. 61-64.