Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Nanoscale Gap Formation and Filling for High-k CMOS Process Integration (NGFFHkCPI)

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Donovan Lee and Tsu-Jae King Liu

The dynamics of nanoscale gap formation are not well understood. Formation rates depend on many parameters including but not limited to: sacrificial material, etch chemistry, temperature, pressure, humidity, aspect ratio, stress environment, chemical transport, etc. This project focuses on the dynamics of making small gaps dependably and predictably for use in semiconductor device modification [1]. Subsequent filling of the nanoscale gaps presents more challenges including but not limited to: high aspect ratio keyholing, material transport, fill uniformity, limitations of ALD, etc. These items are studied with the intention of introducing temperature-sensitive high-k materials into high performance CMOS systems late in a thermal-budgetted process [2].

Figure 1
Figure 1: The goal of this project is to study nanogap formation and dynamics with the intention of refill with a high-k atomic layer deposition for high-performance CMOS gate oxide utilization.

[1]
D. Lee, X. Sun, E. Quevy, R. T. Howe, and T.-J. King, "WetFET--Novel Fluidic Gate-Dielectric Transistor for Sensor Applications," IEEE VLSI-TSA Meeting Technical Digest, 2007, pp. 124-125.
[2]
D. Lee, T. Seidel, J. Dalton, and T.-J. King Liu, "ALD Refill of Nanometer-Scale Gaps with High-k Dielectric for Advanced CMOS Technologies," Electrochemical and Solid-State Letters, Vol 10, Issue 9, 2007, pp. H257-H259.