Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Tribology Test Chip for Contacting NEMS Designs (TTCfCND)

View Current Project Information

Donovan Lee, Roya Maboudian and Tsu-Jae King Liu

A tribology test chip has been simulated, designed, and fabricated in-house. The utilization of a nanoscale gap to accurately control contact area has presented a challenge to processing. Experiments are underway to study the dynamics of sacrificial etching in high aspect ratio nanogaps [1]. Physical metrics observed from these experiments will lead the way for future NEMS logic and switching operations [2,3] as well as provide an in-situ method for surface force analysis.

Figure 1
Figure 1: A typical view of an actuator used to study surface phenomenon. Process development was conducted in the UC Berkeley Microfabrication Laboratory

Figure 2
Figure 2: An adhesion force test structure building-up charge due to electron stagnation at the unreleased point of contact caused by the electron microscope

[1]
D. Lee, T. Seidel, J. Dalton, and T.-J. King Liu, "ALD Refill of Nanometer-Scale Gaps with High-k Dielectric for Advanced CMOS Technologies," Electrochemical and Solid-State Letters, Vol 10, Issue 9, 2007, pp. H257-H259.
[2]
H. Kam, D. Lee, R. T. Howe, and T.-J. King, "A New Nano-Electro-Mechanical Field Effect Transistor (NEMFET) Design for Low-Power Electronics," IEEE International Electron Devices Meeting Technical Digest, 2005, pp. 477-480.
[3]
W. Y. Choi, H. Kam, D. Lee, J. Lai, and T.-J. King Liu, "A Novel Nano-Electro-Mechanical Non-Volatile Memory (NEMory) Device for 3D Integration," IEEE International Electron Devices Meeting, 2007.