Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

A Comprehensive Model of Process Variability for Statistical Timing Optimization

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Kun Qian and Costas J. Spanos

Traditional statistical timing analysis is insufficient for the understanding of process induced circuit performance variations, especially for large critical paths whose variability is controlled by a combination of both random and deterministic effects. Our objective is to create a comprehensive process variability model that properly accounts for these effects, not only locally but also across significant distances.

Certain types of deterministic variations are hierarchical in nature (across wafers, die, etc.) (Figure 1). For example, chamber effects often impart deterministic across-wafer component of variability. These deterministic effects are complemented by random variability that can be modeled as a white noise component. In addition to those large-scale spatial components, there are local random effects such as line-edge roughness and dopant fluctuations.

This project has expanded and modified Pelgrom's model [1] reflecting the hierarchical variability components. We explicitly model the spatial components across die and wafers, while adding both local and global random components. The present model implementation is able to generate statistical distributions of critical path timing and power performance when sizing and placement are known. We are currently investigating interactions between various systematic spatial variations and layout dependent effects to make an accurate prediction from characterization of test structures to circuit variability possible.

Figure 1
Figure 1: Variability architecture: (a) across wafer, (b) wafer to wafer, (c) die to die, (d) across die, (e) layout dependent, and (f) device to device

[1]
M. J. M. Pelgrom, A. C. J. Duinmaiger, and A. P. G. Welbers, "Matching Properties of MOS Transistors," IEEE J. Solid-State Circuits, Vol. 24, October 1989, pp. 1433-1440.