Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Advanced Source/Drain Technologies for Nanoscale CMOS

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Pankaj Kalra and Tsu-Jae King Liu

Challenges for the continued miniaturization of CMOS transistors and hence the semiconductor industry's ability to sustain Moore's Law have received much attention. New materials and processes will be necessary in order to extend transistor scaling to the future CMOS technology node of the ITRS. As the dimensions of a MOSFET are scaled down, parasitic resistance accounts for an increasingly large percentage of the total transistor on-state resistance. Source and drain contact resistance comprise the dominant component of parasitic resistance. The lowest specific contact resistivity reported to date is on the order of 10-8 ohm-cm2, for germanosilicide contact to heavily doped SiGe alloy [1]. Solutions for further lowering specific contact resistivity will be necessary to meet ITRS performance specifications as transistors are scaled below 20 nm gate length.

The objective of this work is to identify means for achieving barrier height < 0.1 eV so as to minimize the impact of contact resistance for sub-20 nm gate length CMOS technologies. Various techniques for reducing the effective Schottky barrier height of a metal-to-semiconductor contact are currently being investigated. We are studying image-force lowering [2] as a possible mechanism to reduce barrier height. The phenomenon of dopant segregation during silicidation achieves very high active dopant concentrations in Si resulting in a large image force field induced barrier lowering at the silicide-semiconductor interface [3]. In most metal-silicon material systems, the barrier height does not correlate well with the metal work function, due to interface states, which pin the Fermi level resulting in a large effective Schottky barrier height. In order to de-pin the Fermi level of the metal, we are investigating passivation of metal-semiconductor interface (eliminating interface states) using species such as Se, S and N. These can be introduced into the semiconductor by ion implantation, and then "piled up" at the silicide-semiconductor interface during the silicidation process.

ITRS further predicts that future CMOS generations will have ultra shallow junctions (USJ) a few nm deep (~10 nm), yet will require sheet resistance on the order of 1000 ohm/sq. in order to keep pace with historical improvement in high performance logic devices. The junction depth requirement stems from the fact that it suppresses short channel effects, and the lower sheet resistance is required to keep the total parasitic resistance of the device within an acceptable degree. These aforementioned requirements will be difficult to meet with conventional doping (ion implantation) and annealing (current rapid thermal processing) techniques.

The demand for a low-energy implant would be increasingly challenging for 45 nm nodes and below because of low throughputs and energy contamination. Various doping techniques have been proposed to counter the limitations of beam-line implantation. Infusion doping is one attractive alternative approach for getting USJs [4]. There is an ongoing effort to investigate the use of molecular implants to extend beam-line implantation to several more generations [5]. The rapid thermal processing is also facing contrasting challenges of dopant movement during annealing and electrical activation limitation due to solid solubility. A higher temperature anneal is desirable but with current RTA tools, the annealing time at these elevated temperatures would be sufficient to cause significant dopant diffusion. For these reasons, alternate methods with shorter annealing time on the order of milli-seconds or below are desirable. Flash and laser annealing are two prime candidates and are often regarded as "diffusion-less" anneals.

We are employing various advanced doping techniques (infusion and molecular implantation) as well as advanced annealing methods (flash and laser) to achieve the USJ targets as set by ITRS for sub 45 nm technology nodes.

[1]
M. Ozturk et al., IEDM Technical Digest, 2002.
[2]
A. Kinoshita, et al., Symp. VLSI Technology Digest, 2004.
[3]
S. M. Sze, Physics of Semiconductor Devices, 2nd ed., New York, Wiley, 1981.
[4]
J. Hautala et al., IWJT, 2006.
[5]
J. Borland et al., IWJT, 2006.