Multi-bit Double-Gate Non-Volatile Memory Device Structures
Alvaro Padilla and Tsu-Jae King Liu
Multiple-gate transistor structures, such as the FinFET structure, have superior electrostatic integrity as compared to conventional planar MOSFETs and are therefore promising for scaling flash memory devices down to sub-50 nm gate lengths. Charge-trap-based non-volatile memory (NVM) devices, such as SONOS cells, avoid floating-gate coupling interference between cells and allow for a thinner tunnel dielectric, hence more aggressive gate-stack equivalent oxide thickness (EOT) scaling, and thus are also preferred for future high-density flash memory technologies. To further enhance storage density with the same technology node, multiple bits can also be stored within a single cell, as previously done with the multi-bit or multi-level storage schemes. Thus, the use of double-gated, charge-trapping, multi-bit NVM cells should allow further scaling of conventional flash memory technologies.
In this work, novel read, program, and erase methods are investigated (via both device simulation and characterization) on both novel and conventional charge-trapping FinFET NVM device structures.