Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

Spacer SRAMs with Improved Robustness

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Andrew Evert Carlson and Tsu-Jae King Liu

Variation in transistor dimensions such as gate length and active width is a serious challenge for SRAM scaling. Because the 6-T SRAM is a symmetric cell, variations of a mismatch, or anti-symmetric, type are particularly detrimental to cell function. Spacer lithography has been shown to define narrow lines with much less variation than e-beam or ashing and trimming of conventional lithography [1]. The regular active and gate layout of SRAM arrays easily accomodates a spacer lithography process, which should yield a more robust SRAM cell. Multiple spacer lithography steps are expected to enable very small SRAM cells and further reduce mismatch.

Y.-K. Choi et al., TED, Vol. 49, No. 3, pp. 436-441.