Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary


View Current Project Information

Andrew Evert Carlson, Zheng Guo, Tsu-Jae King Liu and Borivoje Nikolic

Process variation is an increasing concern for transistor scaling. As transistor dimensions scale down, the variation in parameters such as gate length or channel doping does not scale or increases. For SRAM arrays consisting of several megabits of identical cells, large design margins are required to keep fail counts low. FinFET-based SRAMs have been shown to provide large design margins with reduced susceptibility to process variations [1-3]. FinFET devices with independent front and back gates are expected to provide further enhancement to SRAM read and write margins [3,4]. FinFET SRAMs with independent gating are being fabricated in the UC Berkeley Microlab to demonstrate these results.

T. Park et al., IEDM, 2003, 2.2.
R. Joshi, ESSDERC, 2004, pp. 69-72.
Z. Guo et al., ISLPED, 2005, pp. 2-7.
A. Carlson et al., SOI, 2006, pp. 105-106.