Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

An Integrated Aerial Image Sensor

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Jing Xue and Costas J. Spanos

Semiconductor processing is undergoing a paradigm shift, where ex-situ metrology is replaced by in-line methods, culminating in complete measurement systems integrated on or near the wafer surface. The benefits are tremendous and include improved, high-throughput process monitors, affording a "wafer's eye view" of the process. These methods become necessary as the IC critical dimensions decrease to the deep sub 1/10th micron region, in which the accuracy and precision of measurement has been one of the main limitations of the traditional metrology techniques. In this project, we aim at building a novel integrated aerial image sensor (IAIS) system capable of being integrated into the substrate of autonomous test wafers. The IAIS can be used as a lithography processing monitor. It is expected to provide a more stable metrology platform, higher throughput, lower cost, and be easier and more flexible to deploy. The idea of this design is to use a dark contact mask with moving apertures to capture the incident aerial image near the wafer surface and to use an on-wafer MOS photo-detector to detect this optical signal. Achieving the needed nm-scale resolution is a major challenge, as practical photo-detectors cannot be smaller than a few micrometers. To overcome this challenge, we developed a design involving a series of sub-wavelength spatial phase-shift aperture groups on the wafer surface. These apertures interfere with the aerial image, ultimately forming a low spatial frequency interference (Moiré) pattern, which is captured by m-scale photo-detectors. With sufficient sampling, an aerial image can be reconstructed with a spatial resolution that is much smaller than the size of the photo-detectors. By allowing us to reconstruct the aerial image, the sensor will facilitate several tasks, such as focus calibration, lens aberration estimation, light source analysis, and Critical Dimension (CD) calibration, in a more accurate and efficient manner than current methods.

The near-field optical simulations of this system were done using the Tempest Electromagnetic Simulator. The design parameters, such as aperture width, aperture thickness, the number of aperture groups, the moving steps, and the distance between aperture masks and detectors, etc., have been analyzed and optimized. The simulation also indicates that our sensor system is suitable for the 193 nm immersion lithography environment. Since the near-field diffraction by sub-wavelength apertures requires time-consuming numerical analysis, a library-based matching technique will be used to recompose the image patterns. An on-wafer plane electromagnetic simulation, following the aerial image reconstitution, is done with the Panoramic software to model the partial and total detector image. Lens aberrations, such as defocus, astigmatism, coma, etc., are included in the projection optics. These detailed simulations allow us to predict the ability of IAIS to detect the aerial image under advanced lithography stepper settings.

We are currently using e-beam lithography and plasma etching to pattern the aperture mask. And we are working on the assembly of a commercial CCD with the aperture mask and the holding Si wafer. To this end we use statistical methods to analyze e-beam parameters and therefore to achieve the optimal process window. Also, we are exploring a low temperature polymer bonding technique geared towards serial assembly of a small number of sensors. Another approach that utilizes capillary forces to assist alignment will be explored as a means for high volume parallel assembly of the aerial image transducer in the future.