Ultra-Low Leakage Logic Design Using Pass Transistors (SAPTL)
Louis Poblete Alarcon, Tsung-Te Liu and Jan M. Rabaey
As supply voltages scale with technology, device threshold voltages are forced to decrease in order to achieve the required performance gain due to scaling. However, lowering device threshold voltage increases the leakage or standby current of the overall system.
This leakage energy limits the effectiveness of voltage scaling in reducing the total energy per operation due to the increased delays and reduced activity factors at very low supply voltages.
This project explores the possibility of using a sense amplifier-based pass transistor logic family (SAPTL). Using pass transistor-based logic reduces the number of supply and ground connections in the circuit, thus reducing the amount of leakage current incurred as the device threshold and supply voltages are scaled down.
The SAPTL structure permits both synchronous and self-timed operation, allowing clock power to be included in the overall tradeoff space.
The current phase of this project involves the design and fabrication of test structures for logic block characterization, as well as larger design building blocks such as adders, multipliers, and state machines in 90 nm CMOS.
Figure 1: 90 nm test chip using pass transistor-based logic elements