Reducing the Effects of Parameter Fluctuations in CMOS Circuits
Liang Teck Pang and Borivoje Nikolic
The objective of this research is to investigate the effects of process parameter fluctuations on CMOS performance variations. With an understanding of the characteristics of these fluctuations and their impact on circuits, we hope to develop guidelines and methodologies for circuit design that would mitigate the effects of variations.
We have presented a paper in VLSI Symposium 2006 on the measurement results of a testchip fabricated in 90 nm technology . We measured an array of ring oscillators and S/D leakage currents of NMOS transistors. Our findings show that most variations can be attributed to systematic layout-induced variations and systematic die-to-die variations caused by the manufacturing process. We have also found that orientation of transistor gates and the direction of spacing of gates affect the spatial correlation coefficient.
Presently, we are working on test circuits that measure and characterize SRAM performance variation. We are targeting the experiment on a 45 nm technology.
Figure 1: Die photo of the test-chip
- L. Pang and B. Nikolic, "Impact of Layout on 90 nm CMOS Process Parameter Fluctuations," VLSI Symposium, June 2006.