Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Josephson-CMOS Hybrid Memories

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Qingguo Liu, Kan Fujiwara, Xiaofan Meng, Steven Whiteley and Theodore Van Duzer

Josephson-CMOS hybrid random-access memories have the potential to remove the memory bottleneck faced by Josephson digital technology. The main idea is to use high-density charge-storage MOS memory cells and access them by high-speed superconductive devices. This takes advantage of the best features of each. The operation at 4 K of standard commercial 0.25 mm and 0.18 µm CMOS has been extensively explored and an accurate model has been established. According to the model, operating sub-micron CMOS devices at 4 K will further increase memory circuit speed as well as allow operation at low voltage, resulting in reduced power dissipation. Another important advantage of operating at low temperature is that the leakage currents are substantially suppressed so that there is no need to refresh the memory cells. We have completed extensive simulation of all parts of the 64-kbit hybrid RAM, which includes the interface circuit, decoder, memory cell, and superconducting sensor. The interface circuit is the key part of the memory system. The simulation of the hybrid interface which was proposed last year shows that less than 100 ps delay and 300 mW power consumption can be obtained by designing carefully to minimize parasitics. The total access time for the 64-kb memory system will be less than 0.5 ns according to the simulations when using 0.25 mm CMOS and Josephson current density of xxxx.

Both semiconductor chips and superconductor chips have been fabricated. High speed testing for piggy back structure chip sets using wire bonding have been made for the interface circuit and CMOS memory part. The delays were within 30% of the simulated value. The wire inductance is believed to be the main contributor to the error. A bump-bonding structure has been proposed and the process is being studied preliminarily. By removing the parasitic inductance, more accurate delay time measurements can be done in the near future.

More advanced CMOS and Nb technologies make it possible for faster and denser hybrid memories. Simulations have shown that larger size memories are possible with even better performance.