Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Energy-Performance Optimal Floating Point Unit

View Current Project Information

Seng Oon Toh and Borivoje Nikolic

Existing methods have been developed for optimal gate sizing which have been proven effective in the design of a 64-bit domino logic adder [1]. The goal of this work is to evaluate the scalability and generality of this optimization framework by applying these methods on a larger circuit such as an FPU. The FPU will be synthesized from an RTL description and implemented using standard cells which are optimally sized for minimum energy at a given performance target. A novel retiming algorithm will also be used to further reduce the energy consumed by the sequential circuit without sacrificing performance. The project will culminate in the fabrication of a test-chip that will be used to verify results of the optimization framework.

[1]
S. Kao, R. Zlatanovici, and B. Nikolic, "A 240 ps 64 b Carry-Lookahead Adder in 90 nm CMOS," Solid-State Circuits, 2006 IEEE Int. Conf. Digest of Technical Papers, February 2006, pp. 1735-1744.