Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Circuit Size Optimization with Multiple Sources of Variation and Position Dependent Correlation

View Current Project Information

Qian Ying Tang, Paul David Friedberg and Costas J. Spanos

The growing impact of process variation on circuit performance requires statistical design approaches in which circuits are designed and optimized subject to an estimated variation. Previous work [1] has shown that by including extra margins in each of the gate delays to account for delay variation due to vth variability and optimizing the gate sizes, the circuit delay variation can be reduced by half. Our work addresses the limitations in [1] by delpoying extended models that include delay variations due to vth and effective gate length, as well as spatial correlations between gates, for both variables. These models are used to size a 32-bit ladner-fischer adder and the circuit delay distributions are obtained from Monte Carlo simulations.

The analysis shows that by including the effects of gate length variations and spatial correlations in addition to the original vth variation in the optimization, the standard deviation of the circuit delay decreased from 1.96 in [1] to 1.36, and the circuit yield improved 6% when trying to achieve a 52 nsec maximum acceptable delay. Work is in progress to measure the parameters, such as spatial correlation, used in the optimization in actual state of the art processes, and to extend the optimization scheme for larger circuits.

Figure 1
Figure 1: Histogram of the circuit delay and yield improvements with reference to 52 nsec for different designs: (a) deterministic design, yield is 63%; (b) statistical design that considers only variation due to Vth, yield is 92%; (c) statistical design that considers variations due to both vth and Leff, yield is 96%; (d) statistical design that considers variations due to vth, Leff and position dependant correlation, yield is 98%

[1]
S. Boyd, S.-J. Kim, D. Patil, and M. Horowitz, "A Heuristic Method for Statistical Digital Circuit Sizing," SPIE Int. Symp. Microlithography, February 2006.
[2]
M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching Properties of MOS Transistors," IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, October 1989, pp. 1433-1439.
[3]
P. Friedberg, Y. Cao, J. Cain, R. Wang, J. Rabaey, and C. Spanos, "Modeling Within-Die Gate Length Spatial Correlation for Process-Design Co-Optimization," Design and Process Integration for Microelectronic Manufacturing III, Proceedings of SPIE, Vol. 5675, February 2005.