Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

2008 Research Summary

Power-Performance Tradeoffs In ASICs

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Farhana Sheikh and Borivoje Nikolic

Energy-efficiency has displaced performance as the primary design constraint in optimizing digital integrated circuits. The task of estimating tradeoffs between power (energy) and performance (delay) for each choice of design parameter at each level of design hierarchy is inherently complex and time consuming as it spans a multi-dimensional search space across multiple levels of design abstraction. In this research we explore the use of sensitivity information to systematically and automatically optimize circuits [1,2] in a synthesis-based design environment. A hierarchical, sensitivity-based ASIC design methodology is proposed and demonstrated in the implementation of power-performance optimal signal processing kernels for wireless radio applications. Energy-efficiency gains achieved via this methodology are exploited to accommodate flexibility to support multiple standard wireless radio architectures. Benchmarks include common datapath circuits for embedded circuits such as adders, filters, Viterbi decoders, and cryptography accelerators.

[1]
V. Zyuban and P. Strenski, "Unified Methodology for Resolving Power-Performance Tradeoffs at the Microarchitectural and Circuit Levels," Proc. ISLPED, Monterey, CA, August 12-14, 2002.
[2]
D. Markovic, V. Stojanovic, B. Nikolic, M. A. Horowitz, and R. W. Brodersen, "Methods for True Energy-Performance Optimization," IEEE Journal of Solid-State Circuits, Vol. 39, No. 8, August 2004, pp. 1282-1293.