Engineered High Mobility CMOS Substrates
Haiyan Jin and Nathan W. Cheung
For GeOI fabrication, a large-area Ge layer can be successfully transferred on thermal SiO2/Si receptor wafers by either mechanical-cut or thermal-cut with N2 plasma surface activation.
A new method is presented to extract bulk mobility of Germanium-on-Insulator (GeOI) film based on the data from the depletion mode of a 4-Point-Probe pseudo-MOSFET measurement. Analytical models of the conductance in depletion region and related parameter extraction procedures are presented. This method is validated on both GeOI and SOI substrates prepared by layer transfer.
A pseudo-MOSFET structure was employed to characterize interface trap density, interface fixed charge density, interface carriers mobility, and bulk carrier mobility of these GeOI substrates with various annealing conditions in forming gas ambient. High-temperature annealing in the vicinity of 500°C - 600°C has shown the best carrier mobilities, with the interface trap density as low as 1x1010 q/cm2. The extracted bulk hole mobility of the annealed GeOI is near 500 cm2/V-s, which is higher than that of silicon (300 cm2/V-s) at the same doping concentration level.
For work in progress, we will demonstrate GeOI layer transfer using Ge epi wafers and demonstrate strained GeOI layer transfer. Investigating the characteristic of GeOI with ALD high-K dielectric. We will fabricate FET structures to investigate processing compatibility of Ge devices with CMOS technology.