Double-Gate MOSFET Modeling: Symmetric DG (BSIM)
Mohan Vamsi Dunga, Chung-Hsun Lin, Darsen Duane Lu, Tianjiao Zhang, Chenming Hu and Ali Niknejad
As CMOS scaling is approaching its limits, multi-gate MOSFET (Figure 1) is generating tremendous interest as a possible alternative to the conventional bulk MOSFET. An analytic model for DG MOSFET will enable the circuit design community to evaluate DG MOSFET and use it in various applications. Currently, all the models address only common gate (both gates tied together) operation of a symmetric undoped device. There is a strong need to develop a model for a doped symmetric common device.
In this work, a new surface-potential based model is developed which incorporates the effect of finite body doping on the electrical characteristics of the transistor. Starting from a symmetric DG-FET framework, the model is extended to tri-gate FETs using 3D modeling of SCE. Substrate current model enables the modeling of both SOI FinFETs (Figure 1(a)), and bulk FinFETs (Figure 1(b)). A full-fledged compact model BSIM-CMG has been developed through incorporation of additional physical effects and leakage currents. The model has been verified against TCAD and experimental MG-FET data for long and short channel lengths. Accurate fitting to drain current (Id), transconductance (gm), gm-efficiency (gm/Id), and output conductance (gds) are observed indicating the model efficiency towards digital and analog design applications.
To demonstrate the use of this model, we will continue to explore the simulation of FinFET-based circuits using BSIM-CMG. One example is the variability study of FinFET-based SRAM cells.
Figure 1: Symmetric DG-FETs fabricated on (a) bulk-Si and (b) SOI
Figure 2: I-V and C-V model verification
- M. V. Dunga, C.-H. Lin, D. D. Lu, W. Xiong, C. R. Cleavelin, P. Patruno, J.-R. Huang, F.-L. Yang, A. M. Niknejad, and C. Hu, "BSIM-MG: A Versatile Multi-Gate FET Model for Mixed-Signal Design," Symposium on VLSI Technology, 2007 (Best Student Paper Award).