Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences


UC Berkeley


2008 Research Summary

Modeling the Impact of Manufacturing Variation on Circuit Performance Variability

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Paul David Friedberg, Qian Ying Tang, George Cheng and Costas J. Spanos

Aggressive scaling of silicon technology has enabled dramatic improvements in integrated circuit performance. However, as device parameters are scaled, control of semiconductor manufacturing processes has become increasingly difficult, and variability in circuit performance has worsened. Therefore, the robustness of circuits has emerged as a major roadblock in modern IC design.

In order to combat the growing negative impact of manufacturing variations on circuit performance, two approaches are being taken. The first approach is to apply a renewed focus on process control from a manufacturing perspective, in an effort to directly reduce the variations in device parameters. The second approach comes from the design perspective, where practices can be developed to decrease circuit sensitivity to process variation. This project aims to address the issue of manufacturing variations from both perspectives through the use of a Monte Carlo simulation framework. The simulation framework includes detailed models of spatial variation of gate length over a full-field range of horizontal and vertical separation, based on historical [1] and novel [2] electrical test structure measurements. The Monte Carlo framework will then be used to identify the most effective forms of process control as well as design techniques that mitigate the effects of variations.

Figure 1
Figure 1: Delay variability vs. level of spatial correlation

J. Cain and C. Spanos, "Electrical Linewidth Metrology for Systematic CD Variation Characterization and Causal Analysis," Metrology, Inspection, and Process Control for Microlithography XVII, Proceedings of SPIE, Vol. 5038, 2003, pp. 350-361.
P. Friedberg, W. Cheung, and C. Spanos, "Spatial Variability of Critical Dimensions," VLSI/ULSI Multilevel Interconnection Conference XXII, 2005, pp. 539-546.