Research Areas - Computer Architecture & Engineering (ARC)

Overview

Research to address next generation issues in computer architecture to address the grand challenge of parallel computation, bringing in techniques from other fields (e.g. machine learning for high impact optimizations), ideas for architecture based on novel substrates, power budget issues, micro-architectural circuit level issues, and architectural issues in the development of sensor networks.

Topics

  • ManyCore Parallel Architectures and Systems:

    Given the historic switch to parallelism, the greatest challenge faciing computing is making it easy to write programs that execute efficiently on computing systems with 100s of processors per chip. A multidisplinary team is charting a novel approach based on targetting 13 "dwarfs" that will be the core of future apps instead of benchmarks, relying on "autotuners" instead of compilers, many simple processors instead fewer complex ones, and programming systems inspired more by principles of psychology than by hardware. See view.eecs.berkeley.edu to learn more.

  • Emulation of Highly Parallel Systems (RAMP):

    The Research Accelerator for Multiple Processors (RAMP) project is a multi-univeristy effort to construct a common platform based on FPGAs that will allow researchers to more rapidly persue the goal of easy-to-program, highly efficient, highly-parallel systems. The goal is create a "watering hole effect" by bringing many disciplines together, to ramp up the rate of innovation in parallel systems. See ramp.eecs.berkeley.edu

  • Self aware computing systems:

    Combining machine learning and system architecture: finding and using appropriate probe points in system software to get data to couple to machine learning algorithms for optimized resource use, e.g. predictive power optimization. Applications include power budgets of server farms. Techniques include reinforcement learning and feedback control.

  • Low-power system design:

    Micro-architectures for low power signal processing. Instruction cancellation techniques for low overhead speculative execution. Low-power FPGA design.

  • Reconfigurable computing:

    Instruction set architecture support. Security issues in micro-embedded computing. Probabilistic architecture design.

  • Architecture for novel substrates:

    System design for quantum computing, carbon nano-tube based computers, resistance modulation based GMR switches. Architectures for sensor systems.

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