Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

   

Technical Reports - Alberto L. Sangiovanni-Vincentelli

From Relational Interfaces to Assume-Guarantee Contracts (EECS-2014-21)
Pierluigi Nuzzo, Antonio Iannopollo, Stavros Tripakis and Alberto L. Sangiovanni-Vincentelli

Robust Strategy Synthesis for Probabilistic Systems Applied to Risk-Limiting Renewable-Energy Pricing (EECS-2014-16)
Alberto Alessandro Angelo Puggelli, Alberto L. Sangiovanni-Vincentelli and Sanjit A. Seshia

Data-Driven Probabilistic Modeling and Verification of Human Driver Behavior (EECS-2013-197)
Dorsa Sadigh, Katherine Driggs Campbell, Alberto Alessandro Angelo Puggelli, Wenchao Li, Victor Shia, Ruzena Bajcsy, Alberto L. Sangiovanni-Vincentelli, S. Shankar Sastry and Sanjit A. Seshia

Polynomial-Time Verification of PCTL Properties of MDPs with Convex Uncertainties (EECS-2013-24)
Alberto Alessandro Angelo Puggelli, Wenchao Li, Alberto L. Sangiovanni-Vincentelli and Sanjit A. Seshia

A Tool Integration Approach for Architectural Exploration of Aircraft EPS with Ptolemy II / Metro II (EECS-2013-9)
Hokeun Kim, Liangpeng Guo and Alberto L. Sangiovanni-Vincentelli

The TerraSwarm Research Center (TSRC) (A White Paper) (EECS-2012-207)
Edward A. Lee, John D. Kubiatowicz, Jan M. Rabaey, Alberto L. Sangiovanni-Vincentelli, Sanjit A. Seshia, John Wawrzynek, David Blaauw, Prabal Dutta, Kevin Fu, Carlos Guestrin, Roozbeh Jafari, Doug Jones, Vijay Kumar, Richard Murray, George Pappas, Anthony Rowe, Carl M. Sechen, Tajana Simunic Rosing, Ben Taskar and David Wessel

Efficient Distribution of Triggered Synchronous Block Diagrams (EECS-2011-115)
Yang Yang, Stavros Tripakis and Alberto L. Sangiovanni-Vincentelli

Addressing Modeling Challenges in Cyber-Physical Systems (EECS-2011-17)
Patricia Derler, Edward A. Lee and Alberto L. Sangiovanni-Vincentelli

CalCS: SMT Solving for Non-linear Convex Constraints (EECS-2010-100)
Pierluigi Nuzzo, Alberto Alessandro Angelo Puggelli, Sanjit A. Seshia and Alberto L. Sangiovanni-Vincentelli

A Methodology for Robust System-Level Design: Theoretical Foundations and Preliminary Case-Study (EECS-2009-167)
Pierluigi Nuzzo and Alberto L. Sangiovanni-Vincentelli

W-BOOM: a Framework for Automatic Management of Wireless Sensor Networks in Building Automation and Control (EECS-2009-166)
Pierluigi Nuzzo, Alessandro Pinto and Alberto L. Sangiovanni-Vincentelli

Spatial and Temporal Cost Analysis on OSEK Implementations of Synchronous Reactive Semantics Preserving Communication Protocols (EECS-2008-149)
Guoqiang Wang, Marco Di Natale and Alberto L. Sangiovanni-Vincentelli

COSI: A Public-Domain Design Framework for the Design of Interconnection Networks (EECS-2008-22)
Alessandro Pinto, Luca Carloni and Alberto L. Sangiovanni-Vincentelli

A Methodology and an Open Software Infrastructure for Constraint-Driven Synthesis of On-Chip Communications (EECS-2007-130)
Alessandro Pinto, Alberto L. Sangiovanni-Vincentelli and Luca Carloni

An OSEK/VDX Implementation of Synchronous Reactive Semantics Preserving Communication Protococls (EECS-2007-81)
Guoqiang Wang, Marco Di Natale and Alberto L. Sangiovanni-Vincentelli

Classification, Customization, and Characterization: Using MILP for Task Allocation and Scheduling (EECS-2006-166)
Abhijit Davare, Jike Chong, Qi Zhu, Douglas Michael Densmore and Alberto L. Sangiovanni-Vincentelli

Synthesis of On-Chip Interconnection Structures: From Point-To-Point Links to Networks-on-Chip (EECS-2006-147)
Alessandro Pinto, Luca Carloni and Alberto L. Sangiovanni-Vincentelli

Synthesis of Low Power NOC Topologies under Bandwidth Constraints (EECS-2006-137)
Alessandro Pinto, Luca Carloni and Alberto L. Sangiovanni-Vincentelli

On-Chip Networks Modeling and Simulation (EECS-2006-126)
Qi Zhu, Zhengya Zhang, Alessandro Pinto and Alberto L. Sangiovanni-Vincentelli

Hierarchical Timing Language (EECS-2006-79)
Arkadeb Ghosal, Thomas A. Henzinger, Daniel Iercan, Christoph Kirsch and Alberto L. Sangiovanni-Vincentelli

A Platform-based Design Flow for Kahn Process Networks (EECS-2006-30)
Abhijit Davare, Qi Zhu and Alberto L. Sangiovanni-Vincentelli

Synthesizing FSMs According to co-bu chi Properties (M05/13)
G. Wang, A. Mishchenko, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

METROC: A Metropolis Based Design Methodology Developed in a C++ Framework (M05/6)
D. Gasperini, A. Pinto and Alberto L. Sangiovanni-Vincentelli

Complexity of Two-Level Minimization (M04/45)
C. Umans, T. Villa and Alberto L. Sangiovanni-Vincentelli

Notes on Agent Algebras (M03/38)
J. R. Burch, R. Passerone and Alberto L. Sangiovanni-Vincentelli

Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment (M03/23)
A. Benveniste, L. P. Carloni, P. Caspi and Alberto L. Sangiovanni-Vincentelli

Sequential Synthesis by Language Equation solving (M03/9)
N. Yevtushenko, T. Villa, Robert K. Brayton, A. Petrenko and Alberto L. Sangiovanni-Vincentelli

Maximal Controllers for Hybrid Systems with Multiple Time Event Separations (M03/8)
A. Balluchi, L. Benbenuti, T. Villa, H. Wong-Toi and Alberto L. Sangiovanni-Vincentelli

Describing, Simulating, and Optimizing Hierarchical Bus Scheduling Policies (M03/5)
T. C. Meyerowitz and Alberto L. Sangiovanni-Vincentelli

Seeking Equilibrium between Communication and Computation in System-level Design (M03/24)
Luca P. Carloni and Alberto L. Sangiovanni-Vincentelli

Synthesis of Petri Nets from MSC-based Specifications (M02/38)
M. Sgroi, A. Kondratyev, Y. Watanabe and Alberto L. Sangiovanni-Vincentelli

Logical Analysis of Combinational Cycles (M02/21)
T. R. Shiple, Robert K. Brayton, G. Berry and Alberto L. Sangiovanni-Vincentelli

A Methodology for the Computation of an Upper Bound on Noise Current Spectrum of CMOS Switching Activity (M02/20)
Alessandra Nardi, L. Daniel and Alberto L. Sangiovanni-Vincentelli

Constraint-driven Communications Synthesis (M02/12)
A. Pinto, L. P. Carloni and Alberto L. Sangiovanni-Vincentelli

Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement (M00/66)
W. Gosti, S. P. Khatri and Alberto L. Sangiovanni-Vincentelli

Optimal Control Using Bisimulations (M00/34)
M. Broucke, M.D. Di Benedetto, S. Di Gennard and Alberto L. Sangiovanni-Vincentelli

Hardware and Software Representation, Optimization, and Co-Synthesis for Embedded Systems (M00/7)
B. Tabbara, A. Tabbara and Alberto L. Sangiovanni-Vincentelli

Recycle, Reuse, Reduce (M99/53)
L.P. Carloni and Alberto L. Sangiovanni-Vincentelli

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks (M99/51)
S.P. Khatri, S. Sinha, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A VLSI Design Methodology Using a Network of PLAs Embedded in a Regular Layout Fabric (M99/50)
S.P. Khatri, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Data Flow and Control for Hardware and Software Co-Synthesis in Embedded Systems (M99/31)
B. Tabbara and Alberto L. Sangiovanni-Vincentelli

SPFD-Based Wire Removal in a Network of PLAs (M99/17)
S.P. Khatri, S. Sinha, Andreas Kuehlmann, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A Multi-Layer Area Routing Methodology Using a Boolean Satisfiability Based Router (M99/16)
Y. Jiang, S.P. Khatri, Alberto L. Sangiovanni-Vincentelli and Robert K. Brayton

Routing Techniques for Deep Sub-Micron Technologies (M99/15)
S.P. Khatri, Robert K. Brayton, A. Mehrotra, Alberto L. Sangiovanni-Vincentelli and M.R. Prasad

Latency Insensitive Protocols (M99/11)
L.P. Carloni, K.L. McMillan and Alberto L. Sangiovanni-Vincentelli

Simulation Techniques for Noise in Non-Autonomous Radio Frequency Circuits (M99/10)
A. Mehrotra and Alberto L. Sangiovanni-Vincentelli

Synchronous Equivalence for Embedded Systems: A Tool for Design Exploration (M99/1)
H. Hsieh, F. Balarin and Alberto L. Sangiovanni-Vincentelli

A Layout and Design Methodology for Deep Sub-micron Applications Using Networks of PLAs (M98/68)
S.P. Khatri, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Combinational Verification Revisted (M98/60)
S.P. Khatri, S.C. Krishnan, Alberto L. Sangiovanni-Vincentelli and Robert K. Brayton

Accurate Automatic Timing Characterization of Static CMOS Libraries (M98/58)
S.P. Khatri, Alberto L. Sangiovanni-Vincentelli and Robert K. Brayton

RTL Generation of Hardware Components of a Mixed Hardware/Software Implementation of Embedded Systems for System Level Co-Simulation in VHDL (M98/55)
B. Tabbara, E. Filippi, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

Fast Hardware-Software Co-Simulation Using VHDL Models (M98/54)
B. Tabbara, E. Filippi, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

Multi-Valued Network Compaction Using Redundancy Removal (M98/44)
S.P. Khatri, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Accurate Timing Analysis in the Presence of Cross-Talk Using Timed Automata (M98/25)
S. Tasiran, S.P. Khatri, S. Yovine, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A Noise-Immune VLSI Layout Methodology with Highly Predictable Parasitics (M98/24)
S.P. Khatri, A. Mehrotra, Robert K. Brayton, R.H.J.M. Otten and Alberto L. Sangiovanni-Vincentelli

Quasi-Static Scheduling of Free-Choice Petri Nets (M98/9)
M. Sgroi, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

Deciding State Reachability for Large FSMs (M97/73)
T.R. Shiple, R.K. Ranjan, Alberto L. Sangiovanni-Vincentelli and Robert K. Brayton

Reachability Analysis Using Partitioned- ROBDDs (M97/27)
A. Narayan, A.J. Isles, J. Jain, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Logic Synthesis for Large Pass Transistor Circuits (M97/26)
P. Buch, A. Narayan, A. Richard Newton and Alberto L. Sangiovanni-Vincentelli

Input Encoding for Minimum BDD Size: Theory and Experiments (M97/22)
W. Gosti, T. Villa, A. Saldanha and Alberto L. Sangiovanni-Vincentelli

Co-Design of a Fault-Tolerant Communication Protocol--A Case Study (M97/13)
R. von Hanxleden, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

A Denotational Framework for Comparing Models of Computation (M97/11)
Edward A. Lee and Alberto L. Sangiovanni-Vincentelli

Multi-Valued Decision Diagrams for Logic Synthesis and Verification (M96/75)
T. Kam, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Theory and Algorithms for Face Hypercube Embedding (M96/74)
E. Goldberg, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Trace Driven Logic Synthesis - Application to Power Minimization (M96/62)
L.P. Carloni, P.C. McGeer, A. Saldanha and Alberto L. Sangiovanni-Vincentelli

Generation of a Minimal STG from an Implicit Cover (M96/40)
L. Carloni, T. Villa, T. Kam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

The Tagged Signal Model A Preliminary Version of a Denotational Framework for Comparing Models of Computation (M96/33)
Edward A. Lee and Alberto L. Sangiovanni-Vincentelli

State Minimization of FSM's with Implicit Techniques (M96/17)
T. Villa, T. Kam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Exact Minimization of Binary Decision Diagrams Using Implicit Techniques (M96/16)
A.L. Oliveira, L. Carloni, T. Villa and Alberto L. Sangiovanni-Vincentelli

Evaluation of Trade-Offs in the Design of Embedded Systems Via Co-Simulation (M96/12)
C. Passerone, M. Chiodo, W. Gosti, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

Binary Decision Diagrams on Network of Workstations (M96/9)
J.V. Sanghavi, R.K. Ranjan, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Symbolic Two-Level Minimization (M95/109)
T. Villa, A. Saldanha, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Explicit and Implicit Algorithms for Binate Covering Problems (M95/108)
T. Villa, T. Kam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Theory and Algorithms for State Minimization of Non-Deterministic FSM's (M95/107)
T. Kam, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Implicit Computation of Compatible Sets for State Minimization of ISFSM's (M95/106)
T. Kam, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

VIS: A System for Verification and Synthesis (M95/104)
The VIS Group, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Overcoming Memory Constraints in ROBDD Construction by Functional Decomposition and Partitioning (M95/91)
A. Narayan, S.P. Khatri, J. Jain, M. Fujita, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

High Performance BDD Package Based on Exploiting Memory Hierarchy (M95/81)
R.K. Ranjan, J.V. Sanghavi, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Three-Dimensional Monte Carlo Device Simulation for Massively Parallel Architectures (M95/53)
H. Sheng, R. Guerrieri and Alberto L. Sangiovanni-Vincentelli

Parallel and Distributed Three-Dimensional Monte Carlo Semiconductor Device Simulation (M95/52)
H. Sheng, R. Guerrieri and Alberto L. Sangiovanni-Vincentelli

Compositional Techniques for Mixed Bottom-Up/Top-Down Constructions of ROBDDs (M95/51)
A. Narayan, S.P. Khatri, J. Jain, M. Fujita, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

An Engineering Change Methodology Using Simulation Relations (M95/50)
S.P. Khatri, A. Narayan, S.C. Krishnan, K.L. McMillan, Alberto L. Sangiovanni-Vincentelli and Robert K. Brayton

Combining Top-Down and Bottom-Up Approaches for ROBDD Construction (M95/30)
J. Jain, A. Narayan, C. Coelho, S.P. Khatri, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton and M. Fujita

Advances in Encoding for Logic Synthesis (M95/19)
T. Villa, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

Implicit State Minimization of Non-Deterministic FSM's (M95/18)
T. Kam, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A Methodology for Formal Verification of Real-Time Systems (M95/11)
F. Balarin, Robert K. Brayton, S-T. Cheng, D.A. Kirkpatrick, Alberto L. Sangiovanni-Vincentelli and E.C. Wu

Synthesis of Software Programs for Embedded Control Applications (M94/87)
M. Chiodo, P. Giusto, A. Jurecska, L. Lavagno, K. Suzuki, E. Sentovich, H. Hsieh and Alberto L. Sangiovanni-Vincentelli

Formula-Dependent Equivalence for Compositional CTL Model Checking (M94/78)
A. Aziz, T.R. Shiple, V. Singhal, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A Performance-Driven Router for RF and Microwave Analog Circuit Design (M94/40)
C. Charbon, G. Holmlund, Alberto L. Sangiovanni-Vincentelli and B. Donecker

On the Automatic Computation of Network Invariants (M94/18)
F. Balarin and Alberto L. Sangiovanni-Vincentelli

Sequential Test Pattern Generation: Using Implicit STG Traversal Techniques to Generate Tests and Identify Redundancies in Sequential Circuits (M94/4)
C. Wawrukiewicz, A. Saldanha, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Computing Boolean Expressions with OBDDs (M93/84)
T.R. Shiple, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A Fully Implicit Algorithm for Exact State Minimization (M93/79)
T. Kam, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Implicit Generation of Compatibles for Exact State Minimization (M93/60)
T. Kam, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Heuristic Minimization of BDDs, Using Don't Cares (M93/58)
T.R. Shiple, R. Hojati, Alberto L. Sangiovanni-Vincentelli and Robert K. Brayton

Synthesis of Mixed Software-Hardware Implementations from CFSM Specifications (M93/49)
M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

A Formal Specification Model for Hardware/Software Codesign (M93/48)
M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

Exact Minimum Delay Computation and Clock Frequencies (M93/40)
W.K.C. Lam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions (M93/6)
W.K.C. Lam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Delay Fault Coverage, Test Set Size, and Performance Tradeoffs (M92/119)
W.K. Lam, A. Saldanha, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Design Methods for Reactive Real-Time Systems Codesign (M92/116)
M. Chiodo and Alberto L. Sangiovanni-Vincentelli

Combinational Test Generation Using Satisfiability (M92/112)
P.R. Stephan, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Graph Algorithms for Efficient Clock Schedule Optimization (M92/79)
N. Shenoy, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A Unified Signal Transition Graph Model (M92/78)
A. Yakovlev, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

Delay Models and Sensitization Criteria in the False Path Problem (M92/63)
P. McGeer, A. Saldanha, P.R. Stephan, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Exact Delay Computation with Timed Boolean Functions (M92/57)
W.K.C. Lam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Minimum Cycle Time of Synchronous Circuit with Bounded Delays (M92/56)
W.K.C. Lam, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Automatic Reduction in CTL Compositional Model Checking (M92/55)
M. Chiodo, T.R. Shiple, Alberto L. Sangiovanni-Vincentelli and Robert K. Brayton

SIS: A System for Sequential Circuit Synthesis (M92/41)
E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

A Novel Framework for Solving the State Assignment Problem for Event-Based Specifications (M92/19)
L. Lavagno, C. Moon, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Boolean Matching in Logic Synthesis (M92/15)
H. Savoj, M.J. Silva, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Formal Verification of Timing Constrained Finite-State Systems (M92/8)
F. Balarin and Alberto L. Sangiovanni-Vincentelli

BLIF-MV: An Interchange Format for Design Verification and Synthesis (M91/97)
Robert K. Brayton, M. Chiodo, R. Hojati, T. Kam, K. Kodandapani, R.P. Kurshan, S. Malik, Alberto L. Sangiovanni-Vincentelli, E.M. Sentovich, T. Shiple, K.J. Singh and H.Y. Wang

Synthesis for Testability Techniques for Asynchronous Circuits (M91/77)
Kurt Keutzer, L. Lavagno and Alberto L. Sangiovanni-Vincentelli

A Framework for Satisfying Input and Output Encoding Constraints (M90/110)
A. Saldanha, T. Villa, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Synthesis of Verifiably Hazard-Free Asynchronous Control Circuits (M90/99)
L. Lavagno, Kurt Keutzer and Alberto L. Sangiovanni-Vincentelli

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs (M90/68)
L. Lavagno, S. Malik, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Extended Stuck-Fault Testability for Combinational Networks (M89/87)
R.C. McGeer, Robert K. Brayton, R.L. Rudell and Alberto L. Sangiovanni-Vincentelli

Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques (M89/28)
S. Malik, E.M. Sentovich, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Optimization Techniques for Neural Networks (M89/1)
A.H. Kramer and Alberto L. Sangiovanni-Vincentelli

Encoding Symbolic Inputs for Multi-Level Logic Implementation (M88/69)
S. Malik, Robert K. Brayton and Alberto L. Sangiovanni-Vincentelli

Irredundant Sequential Machines Via Optimal Logic Synthesis (M88/52)
S. Devadas, H.K.T. Ma, A. Richard Newton and Alberto L. Sangiovanni-Vincentelli

A Synthesis and Optimization Procedure for Fully Testable Sequential Machines (M88/14)
S. Devadas, H-K. Tony Ma, A. Richard Newton and Alberto L. Sangiovanni-Vincentelli

Test Generation for Sequential Finite State Machines (M87/36)
H-K. T. Ma, S. Devadas, A. Richard Newton and Alberto L. Sangiovanni-Vincentelli

MOSAICO: An Integrated Macro-Cell Layout System (M87/7)
J. Burns, A. Casotto, M. Igusa, F. Marron, F. Romeo, Alberto L. Sangiovanni-Vincentelli, C. Sechen, H. Shin, G. Srinath and H. Yaghutiel

Computer-Aided Design for VLSI Circuits (M86/16)
A. Richard Newton and Alberto L. Sangiovanni-Vincentelli

Waveform Relaxation: Theory and Practice (M85/65)
J. White, F. Odeh, Alberto L. Sangiovanni-Vincentelli and A. Ruehli

Convergence and Finite-Time Behavior of Simulated Annealing (M85/23)
D. Mitra, F. Romeo and Alberto L. Sangiovanni-Vincentelli

Probabilistic Hill Climbing Algorithms: Properties and Applications (M84/34)
F. Romeo and Alberto L. Sangiovanni-Vincentelli

Modeling and Optimal Control Algorithm Design for HVAC Systems in Energy Efficient Buildings (EECS-2011-12)
Mehdi Maasoumy Haghighi