Designing New Memory Systems for Next-Generation Data Centers (EECS-2022-240)
Howard Mao

Unlocking Design Reuse with Hardware Compiler Frameworks (EECS-2019-168)
Adam Izraelevitz

Energy-Efficient System Design Through Adaptive Voltage Scaling (EECS-2019-146)
Ben Keller

Nested-Parallelism PageRank on RISC-V Vector Multi-Processors (EECS-2019-6)
Alon Amid

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud (EECS-2018-154)
Sagar Karandikar

BOOM v2: an open-source out-of-order RISC-V core (EECS-2017-157)
Christopher Celio, Pi-Feng Chiu, Borivoje Nikolic, David A. Patterson and Krste Asanović

Hardware Acceleration for Memory to Memory Copies (EECS-2017-2)
Howard Mao

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.9.1 (EECS-2016-161)
Andrew Waterman, Yunsup Lee, Rimas Avizienis, David A. Patterson and Krste Asanović

The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V (EECS-2016-130)
Christopher Celio, Daniel Dabbelt, David A. Patterson and Krste Asanović

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.9 (EECS-2016-129)
Andrew Waterman, Yunsup Lee, Rimas Avizienis, David A. Patterson and Krste Asanović

The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1 (EECS-2016-118)
Andrew Waterman, Yunsup Lee, David A. Patterson and Krste Asanović

Productive Design of Extensible On-Chip Memory Hierarchies (EECS-2016-89)
Henry Cook

The Rocket Chip Generator (EECS-2016-17)
Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Daniel Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Ben Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David A. Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo and Andrew Waterman

Mixed Precision Vector Processors (EECS-2015-265)
Albert Ou

Hwacha Preliminary Evaluation Results, Version 3.8.1 (EECS-2015-264)
Yunsup Lee, Colin Schmidt, Sagar Karandikar, Daniel Dabbelt, Albert Ou and Krste Asanović

The Hwacha Microarchitecture Manual, Version 3.8.1 (EECS-2015-263)
Yunsup Lee, Albert Ou, Colin Schmidt, Sagar Karandikar, Howard Mao and Krste Asanović

The Hwacha Vector-Fetch Architecture Manual, Version 3.8.1 (EECS-2015-262)
Yunsup Lee, Colin Schmidt, Albert Ou, Andrew Waterman and Krste Asanović

Opportunities for Fine-Grained Adaptive Voltage Scaling to Improve System-Level Energy Efficiency (EECS-2015-257)
Ben Keller

The RISC-V Compressed Instruction Set Manual, Version 1.9 (EECS-2015-209)
Andrew Waterman, Yunsup Lee, David A. Patterson and Krste Asanović

The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor (EECS-2015-167)
Christopher Celio, David A. Patterson and Krste Asanović

The RISC-V Compressed Instruction Set Manual, Version 1.7 (EECS-2015-157)
Andrew Waterman, Yunsup Lee, David A. Patterson and Krste Asanović

The RISC-V Instruction Set Manual Volume II: Privileged Architecture Version 1.7 (EECS-2015-49)
Andrew Waterman, Yunsup Lee, Rimas Avizienis, David A. Patterson and Krste Asanović

Instruction Sets Should Be Free: The Case For RISC-V (EECS-2014-146)
Krste Asanović and David A. Patterson

Building an Adaptive Operating System for Predictability and Efficiency (EECS-2014-137)
Gage Eads, Juan Colmenares, Steven Hofmeyr, Sarah Bird, Davide Bartolini, David Chou, Brian Glutzman, Krste Asanović and John D. Kubiatowicz

The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0 (EECS-2014-54)
Andrew Waterman, Yunsup Lee, David A. Patterson and Krste Asanović

Resilient Design Methodology for Energy-Efficient SRAM (EECS-2013-37)
Brian Zimmer, Borivoje Nikolic and Krste Asanović

Distributed Memory Breadth-First Search Revisited: Enabling Bottom-Up Search (EECS-2013-2)
Scott Beamer, Aydın Buluc ̧, Krste Asanović and David A. Patterson

Searching for a Parent Instead of Fighting Over Children: A Fast Breadth-First Search Implementation for Graph500 (EECS-2011-117)
Scott Beamer, Krste Asanović and David A. Patterson

The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA (EECS-2011-62)
Andrew Waterman, Yunsup Lee, David A. Patterson and Krste Asanović

SEJITS: Getting Productivity and Performance With Selective Embedded JIT Specialization (EECS-2010-23)
Bryan Catanzaro, Shoaib Ashraf Kamil, Yunsup Lee, Krste Asanović, James Demmel, Kurt Keutzer, John Shalf, Katherine A. Yelick and Armando Fox

Designing Multisocket Systems with Silicon Photonics (EECS-2009-189)
Scott Beamer

Re-architecting DRAM with Monolithically Integrated Silicon Photonics (EECS-2009-179)
Scott Beamer, Chen Sun, Yong-jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic and Krste Asanović

Virtual Local Stores: Enabling Software-Managed Memory Hierarchies in Mainstream Computing Environments (EECS-2009-131)
Henry Cook, Krste Asanović and David A. Patterson

Designing Multi-socket Systems Using Silicon Photonics (EECS-2009-9)
Scott Beamer, Krste Asanović, Chris Batten, Ajay Joshi and Vladimir Stojanovic

The Parallel Computing Laboratory at U.C. Berkeley: A Research Agenda Based on the Berkeley View (EECS-2008-23)
Krste Asanović, Ras Bodik, James Demmel, Tony Keaveny, Kurt Keutzer, John D. Kubiatowicz, Edward A. Lee, Nelson Morgan, George Necula, David A. Patterson, Koushik Sen, John Wawrzynek, David Wessel and Katherine A. Yelick

The Landscape of Parallel Computing Research: A View from Berkeley (EECS-2006-183)
Krste Asanović, Ras Bodik, Bryan Christopher Catanzaro, Joseph James Gebis, Parry Husbands, Kurt Keutzer, David A. Patterson, William Lester Plishker, John Shalf, Samuel Webb Williams and Katherine A. Yelick

RAMP: A Research Accelerator for Multiple Processors (EECS-2006-158)
John Wawrzynek, Mark Oskin, Christoforos Kozyrakis, Derek Chiou, David A. Patterson, Shih-Lien Lu, James C. Hoe and Krste Asanović

RAMP: Research Accelerator for Multiple Processors - A Community Vision for a Shared Experimental Parallel HW/SW Platform (CSD-05-1412)
Arvind, Krste Asanović, Derek Chiou, James C. Hoe, Christoforos Kozyrakis, Shih-Lien Lu, Mark Oskin, David Patterson, Jan Rabaey and John Wawrzynek

The PHiPAC v1.0 Matrix-Multiply Distribution (CSD-98-1020)
Jeff A. Bilmes, Krste Asanović, Chee-Whye Chin and Jim Demmel

Vector Microprocessors (CSD-98-1014)
Krste Asanović

T0 Engineering Data (CSD-97-931)
Krste Asanović and James Beck

Torrent Architecture Manual (CSD-97-930)
Krste Asanović and David Johnson

Development of a Connectionist Network Supercomputer (CSD-93-749)
Krste Asanović, James Beck, Jerry Feldman, Nelson Morgan and John Wawrzynek

CNS-1 Architecture Specification (CSD-93-747)
Krste Asanović, James Beck, Tim Callahan, Jerry Feldman, Bertrand S. Irissou, Brian Kingsbury, Phil Kohn, John Lazzaro, Nelson Morgan, David Stoutamire and John Wawrzynek

Evaluation of a "Stall" Cache: An Efficient Restricted On-chip Instruction Cache (CSD-91-641)
Klaus Erik Schauser, Krste Asanović, David A. Patterson and Edward H. Frank