Michael Zimmer

EECS Department, University of California, Berkeley

Technical Report No. UCB/EECS-2015-181

August 10, 2015

http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-181.pdf

In cyber-physical systems, where embedded computation interacts with physical processes, correctness depends on timing behavior, not just functionality. For high confidence in the timing behavior of real-time embedded software, the underlying hardware must support predictable and isolated task execution. These properties are sacrificed in many conventional processors that use frequent interrupts and hardware prediction mechanisms to improve average-case performance. Mixed-criticality systems—where tasks with different levels of safety criticality are integrated on a single hardware platform to share resources and reduce costs—facilitate complex functionality but further complicate design and verification. The challenge is designing processor architectures that provide high confidence in software functionality and timing behavior without sacrificing processor throughput.

This dissertation presents architectural techniques for task-level trade-offs between predictability, hardware-based isolation, and overall instruction throughput—facilitating the verification of safety-critical tasks and allowing software to meet precise timing constraints. Our processor design, named FlexPRET, uses fine-grained multithreading with flexible hard- ware thread scheduling and integrated timers to evaluate these techniques. With no restrictions on thread interleaving, the hardware thread scheduler executes hard real-time threads (HRTTs) at specific cycles for isolated and predictable behavior and allows soft real-time threads (SRTTs) to use both specific and spare cycles for efficient operation.

A configurable version of FlexPRET is implemented in simulation and on FPGA using Chisel, a hardware construction language that generates both C++ and Verilog code. For a given program path at a constant thread scheduling frequency, the latency of every instruction is constant and known, and the precision of input/output (I/O) instruction timing is bounded. The comparison of FlexPRET with two baseline processors provides the FPGA resource costs of FlexPRET’s microarchitectural features. Using two example applications, we demonstrate a mixed-criticality deployment methodology that provides hardware-based isolation to critical tasks and improves overall instruction throughput by using spare cycles and software scheduling for less critical tasks. FlexPRET can also use software to perform multiple independent I/O operations instead of requiring hardware peripherals.

Advisors: Edward A. Lee

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BibTeX citation:

@phdthesis{Zimmer:EECS-2015-181,
    Author= {Zimmer, Michael},
    Title= {Predictable Processors for Mixed-Criticality Systems and Precision-Timed I/O},
    School= {EECS Department, University of California, Berkeley},
    Year= {2015},
    Month= {Aug},
    Url= {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-181.html},
    Number= {UCB/EECS-2015-181},
    Abstract= {In cyber-physical systems, where embedded computation interacts with physical processes, correctness depends on timing behavior, not just functionality. For high confidence in the timing behavior of real-time embedded software, the underlying hardware must support predictable and isolated task execution. These properties are sacrificed in many conventional processors that use frequent interrupts and hardware prediction mechanisms to improve average-case performance. Mixed-criticality systems—where tasks with different levels of safety criticality are integrated on a single hardware platform to share resources and reduce costs—facilitate complex functionality but further complicate design and verification. The challenge is designing processor architectures that provide high confidence in software functionality and timing behavior without sacrificing processor throughput.

This dissertation presents architectural techniques for task-level trade-offs between predictability, hardware-based isolation, and overall instruction throughput—facilitating the verification of safety-critical tasks and allowing software to meet precise timing constraints. Our processor design, named FlexPRET, uses fine-grained multithreading with flexible hard- ware thread scheduling and integrated timers to evaluate these techniques. With no restrictions on thread interleaving, the hardware thread scheduler executes hard real-time threads (HRTTs) at specific cycles for isolated and predictable behavior and allows soft real-time threads (SRTTs) to use both specific and spare cycles for efficient operation.

A configurable version of FlexPRET is implemented in simulation and on FPGA using Chisel, a hardware construction language that generates both C++ and Verilog code. For a given program path at a constant thread scheduling frequency, the latency of every instruction is constant and known, and the precision of input/output (I/O) instruction timing is bounded. The comparison of FlexPRET with two baseline processors provides the FPGA resource costs of FlexPRET’s microarchitectural features. Using two example applications, we demonstrate a mixed-criticality deployment methodology that provides hardware-based isolation to critical tasks and improves overall instruction throughput by using spare cycles and software scheduling for less critical tasks. FlexPRET can also use software to perform multiple independent I/O operations instead of requiring hardware peripherals.},
}

EndNote citation:

%0 Thesis
%A Zimmer, Michael 
%T Predictable Processors for Mixed-Criticality Systems and Precision-Timed I/O
%I EECS Department, University of California, Berkeley
%D 2015
%8 August 10
%@ UCB/EECS-2015-181
%U http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-181.html
%F Zimmer:EECS-2015-181