Low Dimensional Materials for Next Generation Electronics

Steven Chuang

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2014-65
May 13, 2014

http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-65.pdf

Ever since the invention of the transistor, aggressive channel length scaling has been pursued to achieve higher performance and greater packing density. In order to preserve gate control at short channel lengths, the transistor channel has evolved from bulk to low dimensional substrates, such as 2D thin films and 1D nanowires. For scaling to continue, it is vital that we understand the processing and physics of low dimensional materials.

Chapter 2 focuses on quasi-2D ultrathin body InAsSb-on-insulator n-FETs. III-V materials offer high mobilities for excellent on-state currents, and by using a thin film platform we could potentially obtain good off-state characteristics. Previously we have demonstrated high performance InAs-on-insulator n-FETs. In this study we implement InAsSb transistors on SiO2 and achieve a ~2x enhancement in effective mobility over analogous InAs devices. Top-gated devices are demonstrated with an ION/IOFF of 10^2-10^3 and an intrinsic conductance of ~0.56 mS/um.

1D InAs nanowire (NW) n-FETs are explored in chapter 3. In particular, the nanowire transistors are used to study ballistic transport, the theoretical current density upper limit. We experimentally observe ~ 60nm channel length devices reaching ~80% of the ballistic limit. Length dependent studies on the same nanowire are used to extract a mean free path of ~150nm for the 1st and 2nd electron subbands. We find the mean free path to be independent of temperature, suggesting that surface roughness scattering is the dominant scattering mechanism.

Chapter 4 explores 2D transition metal dichalcogenide (TMDC) thin films. TMDC thin films offer the physical limit of scaling, and ohmic contacts to its conduction and valence bands are required for it to realize low power complementary logic. Previous studies show that elemental metal energy levels are pinned near the conduction band of TMDCs and do not offer effective hole injection. To address this we explore a high work function transition metal oxide, substoichiometric molybdenum trioxide (MoOx), as a hole injection layer to MoS2 and WSe2. MoS2 diodes and p-FETs are demonstrated with MoOx contacts. WSe2 p-FETs with MoOx contacts show a ~10x on-current improvement over devices with Pd contacts.

In chapter 5 we present heterojunction diodes formed by thin films of InAs and WSe2. In traditional epitaxial heterojunctions, the number of possible material combinations are limited by lattice constraints. In this study we overcome this restraint by transferring one layer upon another to form a heterojunction. Specifically, InAs/WSe2 heterojunction diodes are fabricated and measured. A forward/reverse current ratio greater than 10^6, reverse bias current lesser than 10^-12A/um2, and ideality factor of 1.1 are observed.

Advisor: Ali Javey


BibTeX citation:

@phdthesis{Chuang:EECS-2014-65,
    Author = {Chuang, Steven},
    Title = {Low Dimensional Materials for Next Generation Electronics},
    School = {EECS Department, University of California, Berkeley},
    Year = {2014},
    Month = {May},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-65.html},
    Number = {UCB/EECS-2014-65},
    Abstract = {Ever since the invention of the transistor, aggressive channel length scaling has been pursued to achieve higher performance and greater packing density. In order to preserve gate control at short channel lengths, the transistor channel has evolved from bulk to low dimensional substrates, such as 2D thin films and 1D nanowires. For scaling to continue, it is vital that we understand the processing and physics of low dimensional materials. 

Chapter 2 focuses on quasi-2D ultrathin body InAsSb-on-insulator n-FETs. III-V materials offer high mobilities for excellent on-state currents, and by using a thin film platform we could potentially obtain good off-state characteristics. Previously we have demonstrated high performance InAs-on-insulator n-FETs. In this study we implement InAsSb transistors on SiO2 and achieve a ~2x enhancement in effective mobility over analogous InAs devices. Top-gated devices are demonstrated with an ION/IOFF of 10^2-10^3 and an intrinsic conductance of ~0.56 mS/um. 

1D InAs nanowire (NW) n-FETs are explored in chapter 3. In particular, the nanowire transistors are used to study ballistic transport, the theoretical current density upper limit. We experimentally observe ~ 60nm channel length devices reaching ~80% of the ballistic limit. Length dependent studies on the same nanowire are used to extract a mean free path of ~150nm for the 1st and 2nd electron subbands. We find the mean free path to be independent of temperature, suggesting that surface roughness scattering is the dominant scattering mechanism. 

Chapter 4 explores 2D transition metal dichalcogenide (TMDC) thin films. TMDC thin films offer the physical limit of scaling, and ohmic contacts to its conduction and valence bands are required for it to realize low power complementary logic. Previous studies show that elemental metal energy levels are pinned near the conduction band of TMDCs and do not offer effective hole injection. To address this we explore a high work function transition metal oxide, substoichiometric molybdenum trioxide (MoOx), as a hole injection layer to MoS2 and WSe2. MoS2 diodes and p-FETs are demonstrated with MoOx contacts. WSe2 p-FETs with MoOx contacts show a ~10x on-current improvement over devices with Pd contacts. 

In chapter 5 we present heterojunction diodes formed by thin films of InAs and WSe2. In traditional epitaxial heterojunctions, the number of possible material combinations are limited by lattice constraints. In this study we overcome this restraint by transferring one layer upon another to form a heterojunction. Specifically, InAs/WSe2 heterojunction diodes are fabricated and measured. A forward/reverse current ratio greater than 10^6, reverse bias current lesser than 10^-12A/um2, and ideality factor of 1.1 are observed.}
}

EndNote citation:

%0 Thesis
%A Chuang, Steven
%T Low Dimensional Materials for Next Generation Electronics
%I EECS Department, University of California, Berkeley
%D 2014
%8 May 13
%@ UCB/EECS-2014-65
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-65.html
%F Chuang:EECS-2014-65