Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Statistical Verification and Optimization of Integrated Circuits

Yu Ben

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2011-31
April 22, 2011

http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-31.pdf

Semiconductor technology has gone through several decades of aggressive scaling. The ever shrinking size of both transistors and interconnects is necessitating the interaction between the circuit designers and the foundries that fabricate the IC products. In particular, the designers must take into account the impact of the process variability early in the design stage. This includes both the verification and optimization of the circuit with statistical models characterizing the process variability. This thesis advances three frontiers in the variability-aware design flow. Yield estimation is a crucial but expensive verification step in circuit design. Existing methods either suffer from computationally intensive rare event probability calculation, or exhibit poor stability. We investigate the problem by combining partial least squares (PLS) regression, a dimension-reduction technique, with importance sampling, a variance-reduction technique. The simulation results show that the method is able to improve the convergence speed by at least an order of magnitude over existing fast simulation methods, and four orders of magnitude faster than Monte Carlo. In addition to PLS-preconditioned importance sampling, several other methods are also investigated, and their properties are compared. For a quicker verification of the robustness of the circuit, circuit designers often simulate the circuit using corner models. Current corner models are extracted using single transistor performances and cannot incorporate local variability. These facts limit the usage of corner models in deep sub-micron devices and analog applications. We propose to extract the customized corners using PLS regression. The method is tested using ISCAS’85 benchmark circuits. Both the probability density function and cumulative distribution function of the circuit performance predicted by the customized corners agree with Monte Carlo simulation, while delivering two orders of magnitude computational acceleration. The last frontier concerns robust circuit optimization. Most of the existing methods can only deal with a pessimistic worst-case problem. We choose to solve the ideal yield-constrained circuit optimization problem. To this end, we introduce the idea of robust convex approximation to design automation for the first time. Based on the convex approximation, we propose a sequential method to accommodate a realistic, hierarchical variability model. A simple line-search as an outer-loop algorithm is used to control the output the method. The optimization result shows that the proposed method is capable of handling circuits of thousands of gates without performance penalties due to overdesign.

Advisor: Costas J. Spanos


BibTeX citation:

@phdthesis{Ben:EECS-2011-31,
    Author = {Ben, Yu},
    Title = {Statistical Verification and Optimization of Integrated Circuits},
    School = {EECS Department, University of California, Berkeley},
    Year = {2011},
    Month = {Apr},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-31.html},
    Number = {UCB/EECS-2011-31},
    Abstract = {Semiconductor technology has gone through several decades of aggressive scaling. The ever shrinking size of both transistors and interconnects is necessitating the interaction between the circuit designers and the foundries that fabricate the IC products. In particular, the designers must take into account the impact of the process variability early in the design stage. This includes both the verification and optimization of the circuit with statistical models characterizing the process variability. This thesis advances three frontiers in the variability-aware design flow. 
Yield estimation is a crucial but expensive verification step in circuit design. Existing methods either suffer from computationally intensive rare event probability calculation, or exhibit poor stability. We investigate the problem by combining partial least squares (PLS) regression, a dimension-reduction technique, with importance sampling, a variance-reduction technique. The simulation results show that the method is able to improve the convergence speed by at least an order of magnitude over existing fast simulation methods, and four orders of magnitude faster than Monte Carlo. In addition to PLS-preconditioned importance sampling, several other methods are also investigated, and their properties are compared.
For a quicker verification of the robustness of the circuit, circuit designers often simulate the circuit using corner models. Current corner models are extracted using single transistor performances and cannot incorporate local variability. These facts limit the usage of corner models in deep sub-micron devices and analog applications. We propose to extract the customized corners using PLS regression. The method is tested using ISCAS’85 benchmark circuits. Both the probability density function and cumulative distribution function of the circuit performance predicted by the customized corners agree with Monte Carlo simulation, while delivering two orders of magnitude computational acceleration. 
The last frontier concerns robust circuit optimization. Most of the existing methods can only deal with a pessimistic worst-case problem. We choose to solve the ideal yield-constrained circuit optimization problem. To this end, we introduce the idea of robust convex approximation to design automation for the first time. Based on the convex approximation, we propose a sequential method to accommodate a realistic, hierarchical variability model. A simple line-search as an outer-loop algorithm is used to control the output the method. The optimization result shows that the proposed method is capable of handling circuits of thousands of gates without performance penalties due to overdesign.}
}

EndNote citation:

%0 Thesis
%A Ben, Yu
%T Statistical Verification and Optimization of Integrated Circuits
%I EECS Department, University of California, Berkeley
%D 2011
%8 April 22
%@ UCB/EECS-2011-31
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-31.html
%F Ben:EECS-2011-31