Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Scaling of Inkjet-Printed Transistors using Novel Printing Techniques

Huai-Yuan Tseng

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2011-146
December 16, 2011

http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-146.pdf

There has been a great interest in the realization of low-cost electronic applications such as item-level RFID tags and smart labels. Printed electronics has become the most promising technology due to its lithography- and vacuum-free processing. In this regard, solution-processed materials have been advanced rapidly to enhance the performance of printed devices. However, the poor resolution of state-of-the-art printing techniques such as inkjet and gravure printing has necessitated the use of large channel lengths in transistors and large gate to source/drain overlap to compensate for the poor layer-to-layer registration capability. These large dimensions have limited the speed improvement in printed transistors, despite the improvements in materials. Therefore, this thesis focuses on circumventing the printing resolution challenges using novel printing techniques. Scaling of the critical dimensions as well as improvement of the switching speed was achieved with a purely printing process. To reduce the parasitic capacitance of printed transistors, a wetting-based roll-off technique has been applied to achieve self-alignment of transistor source/drain electrodes to the gate, resulting in a minimum overlap. Minimum overlap of 0.47 µm was achieved, contrasted to the >10 µm typically required in conventional printed transistors. The technique has also been applied to realize a fully printed inverter circuit. For further scaling of the transistor dimension, shrinking of the printed gate electrodes is required. Therefore a novel printing technique combining inkjet printing and mechanical pen dragging was proposed. Printed gate lines as narrow as 2.75 µm were demonstrated. Printed transistors combining the highly-scaled gate lines and self-alignment were demonstrated. Transistors with channel lengths as small as 200 nm to 2.75 µm showed the highest cut-off frequency reported to date of 1.6 MHz. The performance is expected to be improved further by using the most advanced materials. This high speed operation will enable the realization of fully printed RFID and other printed applications in the foreseeable future.

Advisor: Vivek Subramanian


BibTeX citation:

@phdthesis{Tseng:EECS-2011-146,
    Author = {Tseng, Huai-Yuan},
    Title = {Scaling of Inkjet-Printed Transistors using Novel Printing Techniques},
    School = {EECS Department, University of California, Berkeley},
    Year = {2011},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-146.html},
    Number = {UCB/EECS-2011-146},
    Abstract = {There has been a great interest in the realization of low-cost electronic applications such as item-level RFID tags and smart labels. Printed electronics has become the most promising technology due to its lithography- and vacuum-free processing. In this regard, solution-processed materials have been advanced rapidly to enhance the performance of printed devices. However, the poor resolution of state-of-the-art printing techniques such as inkjet and gravure printing has necessitated the use of large channel lengths in transistors and large gate to source/drain overlap to compensate for the poor layer-to-layer registration capability.  These large dimensions have limited the speed improvement in printed transistors, despite the improvements in materials. Therefore, this thesis focuses on circumventing the printing resolution challenges using novel printing techniques. Scaling of the critical dimensions as well as improvement of the switching speed was achieved with a purely printing process.
	To reduce the parasitic capacitance of printed transistors, a wetting-based roll-off technique has been applied to achieve self-alignment of transistor source/drain electrodes to the gate, resulting in a minimum overlap.  Minimum overlap of 0.47 µm was achieved, contrasted to the >10 µm typically required in conventional printed transistors. The technique has also been applied to realize a fully printed inverter circuit. For further scaling of the transistor dimension, shrinking of the printed gate electrodes is required. Therefore a novel printing technique combining inkjet printing and mechanical pen dragging was proposed. Printed gate lines as narrow as 2.75 µm were demonstrated.  Printed transistors combining the highly-scaled gate lines and self-alignment were demonstrated. Transistors with channel lengths as small as 200 nm to 2.75 µm showed the highest cut-off frequency reported to date of 1.6 MHz. The performance is expected to be improved further by using the most advanced materials. This high speed operation will enable the realization of fully printed RFID and other printed applications in the foreseeable future.}
}

EndNote citation:

%0 Thesis
%A Tseng, Huai-Yuan
%T Scaling of Inkjet-Printed Transistors using Novel Printing Techniques
%I EECS Department, University of California, Berkeley
%D 2011
%8 December 16
%@ UCB/EECS-2011-146
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-146.html
%F Tseng:EECS-2011-146