Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Power-efficient Design of Multi-Gpbs Wireless Baseband

Ji-Hoon Park and Borivoje Nikolic

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2011-135
December 15, 2011

http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-135.pdf

There is a growing interest in the use of the 7 GHz of unlicensed bandwidth around 60 GHz for high-speed wireless data transfers. Complementary metal-oxide-semiconductor (CMOS) radio frequency (RF) circuits have been demonstrated to effectively operate in this band, but the challenge remains to design a complete high data-rate, energy-efficient system. With data rates of several Gb/s and short wavelengths, the baseband signal processing that compensates for the distortion of the wireless channel presents a significant challenge. This work demonstrates the design of a power-efficient baseband at different levels of abstraction from the algorithm level down to the transistor level. A method for optimizing the equalizer architecture under power and bit-error rate (BER) constraints has been developed. This method has been used to optimize the number of equalizer taps and the distribution of signal processing between analog and digital domains. Two chips were built to demonstrate the methodology based on the IEEE wireless personal area network (WPAN) standard. The first, fully-digital chip implements a single-carrier demodulator that minimizes the power consumption using a parallelized distributed arithmetic architecture. A 2mm x 2mm test chip in a 65 nm CMOS process implements a 6-tap feedforward and 32-tap feedback equalizer for binary phase-shift keying (BPSK) that can be configured to cancel the response of up to 72 symbols while consuming 5.6mW at 2 Gb/s throughput. The second 1.86mm x 1.86mm chip implements a reconfigurable 4-bit ADC and 6-tap analog equalizer in addition to the digital equalizer for quadrature phase-shift keying (QPSK) demodulation. The analog preprocessor is measured to consume 1.3mW for the driver and 300 uW/tap for the analog equalization. The ADC power consumption varies from 1.2mW to 3.8mW depending on the resolution at 1.76 Gs/s. It is shown that, given a BER requirement, the mixed-signal reconfigurable receiver architecture can reduce the total link power consumption compared to a full-digital fixed transceiver depending on the propagation condition.

Advisor: Borivoje Nikolic


BibTeX citation:

@phdthesis{Park:EECS-2011-135,
    Author = {Park, Ji-Hoon and Nikolic, Borivoje},
    Title = {Power-efficient Design of Multi-Gpbs Wireless Baseband},
    School = {EECS Department, University of California, Berkeley},
    Year = {2011},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-135.html},
    Number = {UCB/EECS-2011-135},
    Abstract = {There is a growing interest in the use of the 7 GHz of unlicensed bandwidth around 60 GHz for high-speed wireless data transfers. Complementary metal-oxide-semiconductor
(CMOS) radio frequency (RF) circuits have been demonstrated to effectively operate in this band, but the challenge remains to design a complete high data-rate, energy-efficient system. With data rates of several Gb/s and short wavelengths, the baseband signal processing that compensates for the distortion of the wireless channel presents a significant challenge. This work demonstrates the design of a power-efficient baseband at different levels of abstraction from the algorithm level down to the transistor level.

A method for optimizing the equalizer architecture under power and bit-error rate (BER) constraints has been developed. This method has been used to optimize the number of equalizer taps and the distribution of signal processing between analog and digital domains. Two chips were built to demonstrate the methodology based on the IEEE wireless personal area network (WPAN) standard.

The first, fully-digital chip implements a single-carrier demodulator that minimizes the power consumption using a parallelized distributed arithmetic architecture. A 2mm x 2mm test chip in a 65 nm CMOS process implements a 6-tap feedforward and 32-tap feedback equalizer for binary phase-shift keying (BPSK) that can be configured to cancel the response of up to 72 symbols while consuming 5.6mW at 2 Gb/s throughput.

The second 1.86mm x 1.86mm chip implements a reconfigurable 4-bit ADC and 6-tap analog equalizer in addition to the digital equalizer for quadrature phase-shift keying (QPSK)
demodulation. The analog preprocessor is measured to consume 1.3mW for the driver and 300 uW/tap for the analog equalization. The ADC power consumption varies from 1.2mW
to 3.8mW depending on the resolution at 1.76 Gs/s. It is shown that, given a BER requirement, the mixed-signal reconfigurable receiver architecture can reduce the total link power consumption compared to a full-digital fixed transceiver depending on the propagation condition.}
}

EndNote citation:

%0 Thesis
%A Park, Ji-Hoon
%A Nikolic, Borivoje
%T Power-efficient Design of Multi-Gpbs Wireless Baseband
%I EECS Department, University of California, Berkeley
%D 2011
%8 December 15
%@ UCB/EECS-2011-135
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2011/EECS-2011-135.html
%F Park:EECS-2011-135