Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Intrinsic and Systematic Variability in Nanometer CMOS Technologies

Kedar Patel

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2010-181
December 31, 2010

http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-181.pdf

It has been widely recognized that variability is one the most important challenges to scaling of nanoscale CMOS devices. Intrinsic sources of variation such as discretization effect of dopant atoms, metal-gate work-function variation, and line width roughness threaten an end to scaling realized in the past decades. Line width roughness (LWR) is of great importance as it is a significant fraction of the minimum feature size for nanoscale devices, and it does not scale at the same pace as the minimum feature size. According to previous studies, a complete description of LWR can be provided by three parameters: root-mean square (RMS) roughness ($\si$), correlation length ($\xi$), and roughness exponent ($\al$). A robust method of estimating line width roughness parameters is presented. Specifically, the proposed method provides a {\it better} unbiased estimate of roughness amplitude $\si$ than existing methods. It also provides an estimate of error in LWR parameters. The proposed method also allows for more flexibility in capturing SEM images in that we do not need a special test structure with all lines with same designed CD; any IC layout region with straight lines and arbitrary CDs would suffice. As an application of this method, LWR characteristics of many next-generation lithography processes are explored. LWR parameters are also incorporated in the FinFET device framework, and useful physical insights are provided in regards to its impact on device performance. Variability can also be systematic in nature. Systematic spatial variation can occur at the wafer- or die-level. Accurate estimation of various variability components is necessary for robust circuit design. To this end, a hierarchical decomposition of semiconductor process variation is performed. A holistic discussion on all components of process variation is provided. Specifically, global (inter-die) variation is modeled in a multivariate normal framework. The same framework is extended to enable wafer-selection for model estimation. Least angle regression and agglomerative hierarchical clustering are proposed for selecting wafers for model estimation. Methodologies to model systematic local (intra-die) variation and spatial correlation are provided. Spatial correlation in intra-die observations is extracted using the variogram, and issues in variogram estimation are discussed in detail.

Advisor: Costas J. Spanos


BibTeX citation:

@phdthesis{Patel:EECS-2010-181,
    Author = {Patel, Kedar},
    Title = {Intrinsic and Systematic Variability in Nanometer CMOS Technologies},
    School = {EECS Department, University of California, Berkeley},
    Year = {2010},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-181.html},
    Number = {UCB/EECS-2010-181},
    Abstract = {It has been widely recognized that variability is one the most important challenges to scaling of nanoscale CMOS devices. Intrinsic sources of variation such as discretization effect of dopant atoms, metal-gate work-function variation, and line width roughness threaten an end to scaling realized in the past decades. Line width roughness (LWR) is of great importance as it is a significant fraction of the minimum feature size for nanoscale devices, and it does not scale at the same pace as the minimum feature size. According to previous studies, a complete description of LWR can be provided by three parameters: root-mean square (RMS) roughness ($\si$), correlation length ($\xi$), and roughness exponent ($\al$).

A robust method of estimating line width roughness parameters is presented. Specifically, the proposed method provides a {\it better} unbiased estimate of roughness amplitude $\si$ than existing methods. It also provides an estimate of error in LWR parameters. The proposed method also allows for more flexibility in capturing SEM images in that we do not need a special test structure with all lines with same designed CD; any IC layout region with straight lines and arbitrary CDs would suffice. As an application of this method, LWR characteristics of many next-generation lithography processes are explored. LWR parameters are also incorporated in the FinFET device framework, and useful physical insights are provided in regards to its impact on device performance.

Variability can also be systematic in nature. Systematic spatial variation can occur at the wafer- or die-level.
Accurate estimation of various variability components is necessary for robust circuit design. To this end, a hierarchical decomposition of semiconductor process variation is performed. A holistic discussion on all components of process variation is provided. Specifically, global (inter-die) variation is modeled in a multivariate normal framework. The same framework is extended to enable wafer-selection for model estimation. Least angle regression and agglomerative hierarchical clustering are proposed for selecting wafers for model estimation. Methodologies to model systematic local (intra-die) variation and spatial correlation are provided. Spatial correlation in intra-die observations is extracted using the variogram, and issues in variogram estimation are discussed in detail.}
}

EndNote citation:

%0 Thesis
%A Patel, Kedar
%T Intrinsic and Systematic Variability in Nanometer CMOS Technologies
%I EECS Department, University of California, Berkeley
%D 2010
%8 December 31
%@ UCB/EECS-2010-181
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-181.html
%F Patel:EECS-2010-181