Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

A High-Throughput, Flexible LDPC Decoder for Multi-Gb/s Wireless Personal Area Networks

Matthew Weiner and Borivoje Nikolic

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2010-177
December 22, 2010

http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-177.pdf

This work designs a low-power, high-throughput architecture compatible with any LDPC matrices containing groups of non-overlapping layers, which is a common matrix feature in emerging high-speed wireless standards. It gives a heuristic method for finding a near-optimal architecture and details the structure of each of the decoder’s building blocks. To demonstrate the capabilities of proposed design, an entire decoder compatible with the 802.11ad wireless PAN/LAN standard was created in Simulink using Xilinx System Generator blocks and synthesized using Synopsys’ Design Compiler. For the worst-case matrix, the decoder consumes 42mW at a throughput of 1.5Gb/s and 84mW at a throughput of 3Gb/s.

Advisor: Borivoje Nikolic


BibTeX citation:

@mastersthesis{Weiner:EECS-2010-177,
    Author = {Weiner, Matthew and Nikolic, Borivoje},
    Title = {A High-Throughput, Flexible LDPC Decoder for Multi-Gb/s Wireless Personal Area Networks},
    School = {EECS Department, University of California, Berkeley},
    Year = {2010},
    Month = {Dec},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-177.html},
    Number = {UCB/EECS-2010-177},
    Abstract = {This work designs a low-power, high-throughput architecture compatible with any LDPC matrices containing groups of non-overlapping layers, which is a common matrix feature in emerging high-speed wireless standards. It gives a heuristic method for finding a near-optimal architecture and details the structure of each of the decoder’s building blocks. To demonstrate the capabilities of proposed design, an entire decoder compatible with the 802.11ad wireless PAN/LAN standard was created in Simulink using Xilinx System Generator blocks and synthesized using Synopsys’ Design Compiler. For the worst-case matrix, the decoder consumes 42mW at a throughput of 1.5Gb/s and 84mW at a throughput of 3Gb/s.}
}

EndNote citation:

%0 Thesis
%A Weiner, Matthew
%A Nikolic, Borivoje
%T A High-Throughput, Flexible LDPC Decoder for Multi-Gb/s Wireless Personal Area Networks
%I EECS Department, University of California, Berkeley
%D 2010
%8 December 22
%@ UCB/EECS-2010-177
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2010/EECS-2010-177.html
%F Weiner:EECS-2010-177