Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Design of LDPC Decoders for Improved Low Error Rate Performance

Zhengya Zhang

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2009-99
July 10, 2009

http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-99.pdf

In the past several decades, tremendous progress has been made in both communication theory and practical implementation of communication systems. However, practice often lags the most recent developments in theory possibly for two reasons: the cost of implementation is high, and the practical implementation incurs a non-negligible loss compared to the theoretical bounds. The two objectives of what is theoretically possible and what is achievable by implementation can be better aligned, so theory can be made more relevant and practice can be more powerful and efficient. A novel emulation-simulation framework is presented on studying the low error rate performance of capacity-approaching low-density parity-check (LDPC) codes decoded using a message-passing algorithm. High-throughput hardware emulation uncovers combinatorial error structures that underpin the error floors. The captured errors are analyzed in functionally equivalent software simulation to illuminate the effects of wordlength, quantization, and algorithm design, thereby extending the theoretical discovery for practical usage. The emulation-simulation framework further allows the algorithm and implementation to be iteratively refined to improve the error-floor performance of message-passing decoders. A dual quantization scheme is first introduced to reduce the degradation of soft decoding. Then, a reweighted message-passing algorithm is proposed to eliminate local minima caused by the remaining dominant errors. This improved algorithm is realized in a simple post-processor that compensates the message-passing decoding algorithm to achieve the near maximum-likelihood decoding performance. Results are demonstrated by the design of a 5.35 mm^{2}, 65nm CMOS chip that realizes a grouped parallel architecture to optimize the area and power efficiencies by aggressively scaling down the interconnection overhead. The 47.7 Gb/s LDPC decoder operates without error floor down to the bit error rate level of 10^{−14}. The iterative emulation-simulation framework and systematic architectural exploration can be extended to other complex systems, thereby enabling the joint optimizations of algorithm, architecture, and implementation.

Advisor: Borivoje Nikolic


BibTeX citation:

@phdthesis{Zhang:EECS-2009-99,
    Author = {Zhang, Zhengya},
    Title = {Design of LDPC Decoders for Improved Low Error Rate Performance},
    School = {EECS Department, University of California, Berkeley},
    Year = {2009},
    Month = {Jul},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-99.html},
    Number = {UCB/EECS-2009-99},
    Abstract = {In the past several decades, tremendous progress has been made in both communication theory and practical implementation of communication systems. However, practice often lags the most recent developments in theory possibly for two reasons: the cost of implementation is high, and the practical implementation incurs a non-negligible loss compared to the theoretical bounds. The two objectives of what is theoretically possible and what is achievable by implementation can be better aligned, so theory can be made more relevant and practice can be more powerful and efficient.

A novel emulation-simulation framework is presented on studying the low error rate performance of capacity-approaching low-density parity-check (LDPC) codes decoded using a message-passing algorithm. High-throughput hardware emulation uncovers combinatorial error structures that underpin the error floors. The captured errors are analyzed in functionally equivalent software simulation to illuminate the effects of wordlength, quantization, and algorithm design, thereby extending the theoretical discovery for practical usage.

The emulation-simulation framework further allows the algorithm and implementation to be iteratively refined to improve the error-floor performance of message-passing decoders. A dual quantization scheme is first introduced to reduce the degradation of soft decoding. Then, a reweighted message-passing algorithm is proposed to eliminate local minima caused by the remaining dominant errors. This improved algorithm is realized in a simple post-processor that compensates the message-passing decoding algorithm to achieve the near maximum-likelihood decoding performance. Results are demonstrated by the design of a 5.35 mm^{2}, 65nm CMOS chip that realizes a grouped parallel architecture to optimize the area and power efficiencies by aggressively scaling down the interconnection overhead. The 47.7 Gb/s LDPC decoder operates without error floor down to the bit error rate level of 10^{−14}.

The iterative emulation-simulation framework and systematic architectural exploration can be extended to other complex systems, thereby enabling the joint optimizations of algorithm, architecture, and implementation.}
}

EndNote citation:

%0 Thesis
%A Zhang, Zhengya
%T Design of LDPC Decoders for Improved Low Error Rate Performance
%I EECS Department, University of California, Berkeley
%D 2009
%8 July 10
%@ UCB/EECS-2009-99
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-99.html
%F Zhang:EECS-2009-99