Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

C Code Generation from the Giotto Model of Computation to the PRET Architecture

Shanna-Shaye Forbes, Ben Lickly and Man-Kit Leung

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2009-86
May 28, 2009

http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-86.pdf

We present code generation from the Giotto model of computation in Ptolemy II to the Precision Timed (PRET) Architecture. Giotto is a time-triggered programming model that provides the user with methods to specify timing at a high level, and PRET is a processor architecture that emphasizes predictable timing. The goal of code generation is to automatically generate code that correctly implements the semantics of the model as the designer has specified. We use the ISA-level timing controls of PRET in the C code we generate to fulfill the timing constraints of the Giotto model. We run the generated code on the cycle accurate PRET simulator to verify that our designs meet their deadlines.

Author Comments: This was a class project for the Spring 2009 section of EECS 290N-02 ("Concurrent Models of Computation") with Edward A. Lee.


BibTeX citation:

@techreport{Forbes:EECS-2009-86,
    Author = {Forbes, Shanna-Shaye and Lickly, Ben and Leung, Man-Kit},
    Title = {C Code Generation from the Giotto Model of Computation to the PRET Architecture},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2009},
    Month = {May},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-86.html},
    Number = {UCB/EECS-2009-86},
    Note = {This was a class project for the Spring 2009 section of EECS 290N-02 ("Concurrent Models of Computation") with Edward A. Lee.},
    Abstract = {We present code generation from the Giotto model of computation in Ptolemy II to the Precision Timed (PRET)
Architecture. Giotto is a time-triggered programming model that provides the user with methods to specify timing at a high level, and PRET is a processor architecture that emphasizes predictable timing. The goal of code generation is to automatically generate code that correctly implements the semantics of the model as the designer has specified. We use the ISA-level timing controls of PRET in the C code we generate to fulfill the timing constraints of the Giotto model. We run the generated code on the cycle accurate PRET simulator to verify that our designs meet their
deadlines.}
}

EndNote citation:

%0 Report
%A Forbes, Shanna-Shaye
%A Lickly, Ben
%A Leung, Man-Kit
%T C Code Generation from the Giotto Model of Computation to the PRET Architecture
%I EECS Department, University of California, Berkeley
%D 2009
%8 May 28
%@ UCB/EECS-2009-86
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-86.html
%F Forbes:EECS-2009-86