Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Downconverting Sigma-Delta A/D Converter for a Reconfigurable RF Receiver

Renaldi Winoto and Borivoje Nikolic

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2009-81
May 21, 2009

http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-81.pdf

The proliferation of a multitude of wireless standards as well as the interest in cognitive radios have resulted in the need for a highly reconfigurable radio-frequency (RF) receivers. Reconfigurability in an RF receiver has to be obtained with a negligible degradation in circuit performance, power consumption and silicon area. Digital signal processing offers a degree of flexibility that is perhaps unmatched by analog circuits. Nevertheless, a strategy of processing an RF signal entirely in the digital domain would place an incredible burden in the analog-to-digital converter circuits. A novel receiver architecture is proposed in this work, where a high performance analog-to-digital converter is tightly integrated within the RF circuit. In the proposed architecture, a signal at a radio frequency is directly converted to digital domain using a down-converting sigma-delta (SD) modulator. An SD A/D converter is well-suited for an RF receiver. First, it minimizes aliasing due to the high sampling-rate. Second, it enables high-resolution conversion of the desired signal with low-resolution components. A direct-conversion to DC architecture greatly simplifies frequency planning of this flexible receiver, as it eliminates problems related to image frequency bands. A circuit prototype demonstrating the proposed concept has been designed, fabricated and measured. The test-chip prototype is able to maintain an SNR of greater than +59dB across a 4-MHz bandwidth with a programmable center frequency of 400MHz to 1.7GHz. As illustrated in this work, the tight integration of the SD modulator within the RF receiver also enables the receiver to achieve a very good linearity. An IIP3 of +19dBm and an out-of-band 3-dB desensitization level of +6dBm is measured in this test-chip prototype.

Advisor: Borivoje Nikolic


BibTeX citation:

@phdthesis{Winoto:EECS-2009-81,
    Author = {Winoto, Renaldi and Nikolic, Borivoje},
    Title = {Downconverting Sigma-Delta A/D Converter for a Reconfigurable RF Receiver},
    School = {EECS Department, University of California, Berkeley},
    Year = {2009},
    Month = {May},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-81.html},
    Number = {UCB/EECS-2009-81},
    Abstract = {The proliferation of a multitude of wireless standards as well as the interest in cognitive radios have resulted in the need for a highly reconfigurable radio-frequency (RF) receivers. Reconfigurability in an RF receiver has to be obtained with a negligible degradation in circuit performance, power consumption and silicon area. Digital signal processing offers a degree of flexibility that is perhaps unmatched by analog circuits. Nevertheless, a strategy of processing an RF signal entirely in the digital domain would place an incredible burden in the analog-to-digital converter circuits.

A novel receiver architecture is proposed in this work, where a high performance analog-to-digital converter is tightly integrated within the RF circuit. In the proposed architecture, a signal at a radio frequency is directly converted to digital domain using a down-converting sigma-delta (SD) modulator. An SD A/D converter is well-suited for an RF receiver. First, it minimizes aliasing due to the high sampling-rate. Second, it enables high-resolution conversion of the desired signal with low-resolution components.  A direct-conversion to DC architecture greatly simplifies frequency planning of this flexible receiver, as it eliminates problems related to image frequency bands.

A circuit prototype demonstrating the proposed concept has been designed, fabricated and measured. The test-chip prototype is able to maintain an SNR of greater than +59dB across a 4-MHz bandwidth with a programmable center frequency of 400MHz to 1.7GHz. As illustrated in this work, the tight integration of the SD modulator within the RF receiver also enables the receiver to achieve a very good linearity. An IIP3 of +19dBm and an out-of-band 3-dB desensitization level of +6dBm is measured in this test-chip prototype.}
}

EndNote citation:

%0 Thesis
%A Winoto, Renaldi
%A Nikolic, Borivoje
%T Downconverting Sigma-Delta A/D Converter for a Reconfigurable RF Receiver
%I EECS Department, University of California, Berkeley
%D 2009
%8 May 21
%@ UCB/EECS-2009-81
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-81.html
%F Winoto:EECS-2009-81