0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VII.
Laszlo Petho
EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2009-163
December 7, 2009
http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-163.pdf
This report details the fifth six-inch baseline run, CMOS192, fabricated in the UC Berkeley Microlab. A moderately complex 0.35 µm twin-well process, developed and fine-tuned in earlier runs, was used. Different research circuits were placed in the drop-in area: ring oscillators, different memory circuits, a MEMS design, features for carbon nanotube integration and nanowire-based molecular sensors.
BibTeX citation:
@techreport{Petho:EECS-2009-163,
Author = {Petho, Laszlo},
Title = {0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VII.},
Institution = {EECS Department, University of California, Berkeley},
Year = {2009},
Month = {Dec},
URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-163.html},
Number = {UCB/EECS-2009-163},
Abstract = {This report details the fifth six-inch baseline run, CMOS192, fabricated in the UC Berkeley Microlab. A moderately complex 0.35 µm twin-well process, developed and fine-tuned in earlier runs, was used. Different research circuits were placed in the drop-in area: ring oscillators, different memory circuits, a MEMS design, features for carbon nanotube integration and nanowire-based molecular sensors.}
}
EndNote citation:
%0 Report %A Petho, Laszlo %T 0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VII. %I EECS Department, University of California, Berkeley %D 2009 %8 December 7 %@ UCB/EECS-2009-163 %U http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-163.html %F Petho:EECS-2009-163