Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Elimination of Side Channel attacks on a Precision Timed Architecture

Isaac Liu and David McGrogan

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2009-15
January 26, 2009

http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-15.pdf

Side-channel attacks exploit information-leaky implementations of cryptographic algorithms to find the encryption key. These information leaks are caused by the underlying execution platform which contains hardware elements designed to optimize performance at the expense of predictable execution time. This shows that for security systems, not only does the software need to be secure, but the execution platform also needs to be secure in order for the entire system to be truly secure. PRET is an architecture designed for real time systems that has total predictability without sacrificing performance. It contains ISA extensions to bring total control over a program's temporal properties to the software level. We show that this design can not only defend against all software side channel attacks on encryption algorithms, but completely eliminate the root cause of the problem. We demonstrate this by running a reference implementation of the RSA algorithm on PRET and proving its immunity to side channel attacks.

Author Comments: This a class project report describing early work on eliminating side channel attacks using PRET


BibTeX citation:

@techreport{Liu:EECS-2009-15,
    Author = {Liu, Isaac and McGrogan, David},
    Title = {Elimination of Side Channel attacks on a Precision Timed Architecture},
    Institution = {EECS Department, University of California, Berkeley},
    Year = {2009},
    Month = {Jan},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-15.html},
    Number = {UCB/EECS-2009-15},
    Note = {This a class project report describing early work on eliminating side channel attacks using PRET},
    Abstract = {Side-channel attacks exploit information-leaky implementations of cryptographic algorithms to find the encryption key. These information leaks are caused by the underlying execution platform which contains hardware elements designed to optimize performance at the expense of predictable execution time. This shows that for security systems, not only does the software need to be secure, but the execution platform also needs to be secure in order for the entire system to be truly secure. PRET is an architecture designed for real time systems that has total predictability without sacrificing performance. It contains ISA extensions to bring total control over a program's temporal properties to the software level. We show that this design can not only defend against all software side channel attacks on encryption algorithms, but completely eliminate the root cause of the problem. We demonstrate this by running a reference implementation of the RSA algorithm on PRET and proving its immunity to side channel attacks.}
}

EndNote citation:

%0 Report
%A Liu, Isaac
%A McGrogan, David
%T Elimination of Side Channel attacks on a Precision Timed Architecture
%I EECS Department, University of California, Berkeley
%D 2009
%8 January 26
%@ UCB/EECS-2009-15
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2009/EECS-2009-15.html
%F Liu:EECS-2009-15