Electrical Engineering
      and Computer Sciences

Electrical Engineering and Computer Sciences

COLLEGE OF ENGINEERING

UC Berkeley

Advanced Source/Drain Technologies for Nanoscale CMOS

Pankaj Kalra

EECS Department
University of California, Berkeley
Technical Report No. UCB/EECS-2008-95
August 15, 2008

http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-95.pdf

Transistor scaling has been the driving force for technology advancements in the semiconductor industry over the last few decades. In order to mitigate short channel effects, the gate-oxide thickness and source/drain junction depth have been scaled along with the gate length. Recently, however, gate-oxide thickness scaling has slowed, as evidenced by the fact that an equivalent oxide thickness (EOT) of ~1 nm has been used for the past 2-3 generations of CMOS technology. Although significant progress has been made in the development of high-permittivity (high-k) gate-dielectric materials and metal gate technology in recent years, it will be difficult to scale EOT well below 1 nm. This makes junction-depth scaling even more pressing for continued transistor scaling. Furthermore, as the dimensions of MOSFETs are scaled down, the contact resistance of silicide-to-source/drain regions increasingly limits transistor performance. This is because the on-state resistance of a MOSFET drops with transistor scaling, whereas contact resistance increases with contact area scaling. Contact resistance increases exponentially with Schottky barrier height (SBH) of the silicide-to-semiconductor contact. Thus, lower values of SBH will be needed in order to achieve substantial performance improvements with transistor scaling in the future. In practice, fermi-level pinning makes it especially difficult to attain low values of SBH for metal (silicide) contact to n-type silicon. This dissertation addresses the aforementioned scaling challenges associated with the design of source/drain structures for sub-45 nm CMOS generations. Firstly, the progress made towards the formation of ultra-shallow junctions with the help of advanced annealing techniques, low-energy implants, and GCIB doping is presented. The experimental results obtained with flash annealing indicate that it is possible to achieve sub-15 nm junctions with lower sheet resistance (~1000 Ω/sq.), adequate for 32 nm CMOS technology. Since high-k/metal-gate stacks are already used in the most advanced 45 nm CMOS technology today, it is important to assess the compatibility of flash annealing with high-k/metal-gate stacks. The process integration of high-k/metal-gate stacks with flash annealing is discussed next. It is shown that the flash annealing process has minimal effects on gate stack properties and is found to be compatible with the high-k/metal-gate stacks. However, it results in degraded interface quality which is improved by using a post-metallization anneal. To reduce the effective SBH of silicide-to-semiconductor contact, various species (nitrogen, fluorine, sulfur and selenium) are studied. These species were implanted into the semiconductor, and then piled up at the silicide-semiconductor interface during the silicidation process. It is shown that significant SBH lowering (by as much as 0.37 eV) can be achieved on n-type silicon using nitrogen. The impact of this process on the properties of NiSi is assessed and the mechanism of SBH reduction is explained. Encouraging results are also obtained with sulfur and selenium, and a comparison of effective SBH reduction is made for all studied species. Finally, material properties of nickel germanide formed on epi-Ge on Si substrate are studied to form low-resistance and thermally stable contact material for realizing highly-scaled high-performance technology based on Ge-channel MOSFETs.

Advisor: Tsu-Jae King Liu


BibTeX citation:

@phdthesis{Kalra:EECS-2008-95,
    Author = {Kalra, Pankaj},
    Title = {Advanced Source/Drain Technologies for Nanoscale CMOS},
    School = {EECS Department, University of California, Berkeley},
    Year = {2008},
    Month = {Aug},
    URL = {http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-95.html},
    Number = {UCB/EECS-2008-95},
    Abstract = {Transistor scaling has been the driving force for technology advancements in the semiconductor industry over the last few decades. In order to mitigate short channel effects, the gate-oxide thickness and source/drain junction depth have been scaled along with the gate length. Recently, however, gate-oxide thickness scaling has slowed, as evidenced by the fact that an equivalent oxide thickness (EOT) of ~1 nm has been used for the past 2-3 generations of CMOS technology. Although significant progress has been made in the development of high-permittivity (high-k) gate-dielectric materials and metal gate technology in recent years, it will be difficult to scale EOT well below 1 nm. This makes junction-depth scaling even more pressing for continued transistor scaling. Furthermore, as the dimensions of MOSFETs are scaled down, the contact resistance of silicide-to-source/drain regions increasingly limits transistor performance. This is because the on-state resistance of a MOSFET drops with transistor scaling, whereas contact resistance increases with contact area scaling. Contact resistance increases exponentially with Schottky barrier height (SBH) of the silicide-to-semiconductor contact. Thus, lower values of SBH will be needed in order to achieve substantial performance improvements with transistor scaling in the future. In practice, fermi-level pinning makes it especially difficult to attain low values of SBH for metal (silicide) contact to n-type silicon. This dissertation addresses the aforementioned scaling challenges associated with the design of source/drain structures for sub-45 nm CMOS generations. 

Firstly, the progress made towards the formation of ultra-shallow junctions with the help of advanced annealing techniques, low-energy implants, and GCIB doping is presented. The experimental results obtained with flash annealing indicate that it is possible to achieve sub-15 nm junctions with lower sheet resistance (~1000 Ω/sq.), adequate for 32 nm CMOS technology. 
 
Since high-k/metal-gate stacks are already used in the most advanced 45 nm CMOS technology today, it is important to assess the compatibility of flash annealing with high-k/metal-gate stacks. The process integration of high-k/metal-gate stacks with flash annealing is discussed next. It is shown that the flash annealing process has minimal effects on gate stack properties and is found to be compatible with the high-k/metal-gate stacks. However, it results in degraded interface quality which is improved by using a post-metallization anneal.

To reduce the effective SBH of silicide-to-semiconductor contact, various species (nitrogen, fluorine, sulfur and selenium) are studied. These species were implanted into the semiconductor, and then piled up at the silicide-semiconductor interface during the silicidation process. It is shown that significant SBH lowering (by as much as 0.37 eV) can be achieved on n-type silicon using nitrogen. The impact of this process on the properties of NiSi is assessed and the mechanism of SBH reduction is explained. Encouraging results are also obtained with sulfur and selenium, and a comparison of effective SBH reduction is made for all studied species. Finally, material properties of nickel germanide formed on epi-Ge on Si substrate are studied to form low-resistance and thermally stable contact material for realizing highly-scaled high-performance technology based on Ge-channel MOSFETs.}
}

EndNote citation:

%0 Thesis
%A Kalra, Pankaj
%T Advanced Source/Drain Technologies for Nanoscale CMOS
%I EECS Department, University of California, Berkeley
%D 2008
%8 August 15
%@ UCB/EECS-2008-95
%U http://www.eecs.berkeley.edu/Pubs/TechRpts/2008/EECS-2008-95.html
%F Kalra:EECS-2008-95